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PDF S1216AATA-75-E Data sheet ( Hoja de datos )
| Número de pieza | S1216AATA-75-E | |
| Descripción | EDS1216AATA-75-E | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
128M bits SDRAM
EDS1216AATA (8M words × 16 bits)
Description
The EDS1216AATA is a 128M bits SDRAM organized
as 2,097,152 words × 16 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 54-pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
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Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0411E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
DataSheet4 U .com
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1 page  
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EDS1216AATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol Grade
max.
Unit
Test condition
Operating current
IDD1
100 mA
Burst length = 1
tRC = tRC (min.)
Standby current in power down
IDD2P
3
mA
CKE = VIL,
tCK = tCK (min.)
Standby current in power down
(input signal stable)
IDD2PS
2 mA CKE = VIL, tCK = ∞
Standby current in non power down
IDD2N
20
mA
CKE, /CS = VIH,
tCK = tCK (min.)
Standby current in non power down
(input signal stable)
IDD2NS
9
mA
CKE = VIH, tCK = ∞,
/CS = VIH
Active standby current in power down
IDD3P
4
mA
CKE = VIL,
tCK = tCK (min.)
Active standby current in power down
(input signal stable)
IDD3PS
3 mA CKE = VIL, tCK = ∞
Active standby current in non power down IDD3N
40
mA
CKE, /CS = VIH,
tCK = tCK (min.)
Active standby current in non power down
(input signal stable)
IDD3NS
25
mA
CKE = VIH, tCK = ∞,
/CS = VIH
Burst operating current
IDD4
120 mA
tCK = tCK (min.),
BL = 4
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
Refresh current
IDD5
220 mA
tRC = tRC (min.)
3
Self refresh current
IDD6
1.5
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
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Data Sheet E0411E40 (Ver. 4.0)
DataSheet4 U .com
5
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5 Page 
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EDS1216AATA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
L
Bank 1
H
Bank 2
L
Bank 3
H
www.DataSRheemet4aUrk.c: omH: VIH. L: VIL.
BA1
L
L
H
H
UDQM and LDQM (input pins)
UDQM and LDQM control input/output buffers. UDQM and LDQM control upper byte (DQ8 to DQ15) and lower byte
(DQ0 to DQ7).
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0411E40 (Ver. 4.0)
DataSheet4 U .com
11
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