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PDF KM68512A Data sheet ( Hoja de datos )
| Número de pieza | KM68512A | |
| Descripción | 64Kx8 bit Low Power CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KM68512A Family
Document Title
64Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
History
Initial draft
0.1 Revision
1.0 Finalize
2.0 Revision
- Add 45ns part with 30pf test load.
3.0 Revision
- Change Data Sheet format :
One data sheets for industrial and commercial product
4.0 Revision
- Change Data Sheet format
- Remove 45ns part from commercial product and 100ns part
from industrial product
- Remove low power part form TSOP package
Draft Data
Novemer 28, 1993
May 13, 1994
December 1, 1994
August 12, 1995
April 15, 1996
January 9, 1998
Remark
Design target
Preliminary
Final
Final
Final
Final
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The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 4.0
January 1997
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1 page  
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KM68512A Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C)
Read
Write
Speed Bins
Parameter List
Symbol
55ns
70ns
Min Max Min Max
Read cycle time
tRC 55 - 70 -
Address access time
tAA - 55 - 70
Chip select to output
tCO1, tCO2 - 55 - 70
Output enable to valid output
tOE - 25 - 35
Chip select to low-Z output
tLZ 10 - 10 -
Output enable to low-Z output
tOLZ 5 - 5 -
Chip disable to high-Z output
tHZ 0 20 0 25
Output disable to high-Z output
tOHZ
0 20 0 25
Output hold from address change
tOH 10 - 10 -
Write cycle time
tWC 55 - 70 -
Chip select to end of write
tCW 45 - 60
www.DataSheet4U.comAddress set-up time
tAS 0 - 0
Address valid to end of write
tAW 45 - 60
-
-
-
Write pulse width
tWP 40 - 50 -
Write recovery time
tWR 0 - 0 -
Write to output high-Z
tWHZ
0 20 0 25
Data to write time overlap
tDW 25 - 30 -
Data hold from write time
tDH 0 - 0 -
End write to output low-Z
tOW 5 - 5 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
KM68512AL/L-L
IDR
KM68512ALI/LI-L
tSDR
tRDR
Test Condition
CS11)≥Vcc-0.2V
Vcc=3.0V CS1≥Vcc-0.2V
CS2≥Vcc-0.2V or CS2≤0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
See data retention waveform
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled).
Min Typ Max Unit
2.0 - 5.5 V
- 1 50
- 0.5 10 µA
- - 50
- - 25
0- -
ms
5- -
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5 Revision 4.0
January 1997
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5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KM68512A.PDF ] | |
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