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PDF L80227 Data sheet ( Hoja de datos )
| Número de pieza | L80227 | |
| Descripción | Single chip 100BaseTX/10BaseT PHY | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L80227 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TECHNICAL
MANUAL
L80227
www.D1a0tBaASSEh-eT/et4U.com
100BASE-TX
Ethernet PHY
October 2002
®
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1 page  
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PRE
R/LH
R/LHI
R/LL
R/LLI
R/LT
R/LTI
R/WSC
RFC
RJ-45
RMON
SA
SFD
SNMP
SOI
SSD
STP
TP
µH
µP
UTP
Preamble
Read Latched High
Read Latched High with Interrupt
Read Latched Low
Read Latched Low with Interrupt
Read Latched Transition
Read Latched Transition with Interrupt
Read/Write Self Clearing
Request for Comments
Registered Jack-45
Remote Monitoring
Start Address or Station Address
Start of Frame Delimiter
Simple Network Management Protocol
Start of Idle
Start of Stream Delimiter
Shielded Twisted Pair
Twisted Pair
microhenry
microprocessor
Unshielded Twisted Pair
www.DataSheet4U.comConventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Preface
v
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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5 Page 
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Figures
1.1 Top Level Block Diagram
2.1 L80227 Device Block Diagram
2.2 100BASE-TX and 10BASE-T Frame Format
2.3 MII Frame Format
2.4 TP Output Voltage Template
2.5 TP Input Voltage Template (10 Mbits/s)
2.6 Link Pulse Output Voltage Template (10 Mbits/s)
2.7 NLP vs FLP Link Pulse
2.8 SOI Output Voltage Template (10 Mbits/s)
3.1 Device Logic Diagram
5.1 MI Serial Port Frame Timing Diagram
5.2 MI Serial Frame Structure
6.1 25 MHz Output Timing
6.2 Transmit Timing (100 Mbits/s)
6.3 Transmit Timing (10 Mbits/s)
6.4 Receive Timing, Start of Packet (100 Mbits/s)
6.5 Receive Timing, End of Packet (100 Mbits/s)
6.6 Receive Timing, Start of Packet (10 Mbits/s)
www.DataSheet4U.com6.7 Receive Timing, End of Packet (10 Mbits/s)
6.8 RX_EN Timing
6.9 Collision Timing, Receive (100 Mbits/s)
6.10 Collision Timing, Receive (10 Mbits/s)
6.11 Collision Timing, Transmit (100 Mbits/s)
6.12 Collision Timing, Transmit (10 Mbits/s)
6.13 Collision Test Timing
6.14 NLP Link Pulse Timing
6.15 FLP Link Pulse Timing
6.16 Jabber Timing
6.17 MI Serial Port Timing
6.18 L80227 64-Pin LQFP, Top View
6.19 64-Pin LQFP Package Drawing
A.1 Typical Network Interface Adapter Card Schematic Using
the L80227
A.2 Typical Switching Port Schematic Using L80227
A.3 Typical External PHY Schematic Using L80227
A.4 MII Output Driver Characteristics
1-2
2-4
2-5
2-6
2-17
2-19
2-23
2-24
2-33
3-2
5-3
5-4
6-7
6-9
6-10
6-13
6-13
6-14
6-15
6-15
6-17
6-17
6-18
6-18
6-18
6-23
6-24
6-25
6-26
6-33
6-34
A-2
A-3
A-4
A-10
xi
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L80227.PDF ] | |
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