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PDF DS1867 Data sheet ( Hoja de datos )
| Número de pieza | DS1867 | |
| Descripción | Dual Digital Potentiometer with EEPROM | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS1867
Dual Digital Potentiometer with EEPROM
FEATURES
PIN ASSIGNMENT
§ Nonvolatile version of the popular DS1267
§ Low power consumption, quiet, pumpless
VB 1
14 VCC
design
§ Operates from single 5V or ±5V supplies
§ Two digitally controlled, 256-position
H1 2
L1 3
W1 4
13 SOUT
12 WO
11 HO
potentiometers
§ Wiper position is maintained in the absence of
power
§ Serial port provides means for setting and
RST
CLK
GND
5
6
7
10 LO
9 COUT
8 DQ
reading both potentiometers
§ Resistors can be connected in series to
14-Pin DIP (300-mil)
See Mech. Drawings Section
provide increased total resistance
§ 16-pin SOIC and 20-pin TSSOP for surface
VB 1
16 VCC
mount applications
NC 2
15 NC
§ Standard resistance values:
www.DataSheet4U.com- DS1867-10 ~ 10 kΩ
H1 3
L1 4
14 SOUT
13 WO
- DS1867-50 ~ 50 kΩ
W1 5
12 HO
- DS1867-100 ~ 100 kΩ
§ Operating Temperature Range:
- Industrial: -40°C to +85°C
RST
CLK
GND
6
7
8
11 LO
10 COUT
9 DQ
PIN DESCRIPTION
L0, L1 - Low End of Resistor
H0, H1 - High End of Resistor
W1, W2 - Wiper End of Resistor
VB
SOUT
- Substrate Bias
- Wiper for Stacked Configuration
RST - Serial Port Reset Input
DQ - Serial Port Data Input
CLK
- Serial Port Clock Input
COUT
VCC
GND
- Cascade Serial Port Output
- +5-Volt Supply Input
- Ground
NC - No Internal Connection
DNC
- Do Not Connect
16-Pin SOIC (300-mil)
See Mech. Drawings Section
VB
NC
H1
L1
W1
RST
CLK
DNC
DNC
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 DNC
18 DNC
17 SOUT
16 WO
15 HO
14 LO
13 COUT
12 DNC
11 DQ
20-Pin TSSOP (173-mil)
See Mech. Drawings Section
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I/O SHIFT REGISTER Figure 3
DS1867
17-BIT I/O SHIFT REGISTER
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value (see Figure 2(a)).
When wiper position data is to be written to the DS1867, 17-bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the
register incomplete and possibly an error in desired wiper position. After a communication transaction
has been completed the RST signal input should be taken to a low state to prevent any inadvertent
changes to the device shift register. Once RST has reached a low state, the contents of the I/O shift
register are loaded into the respective multiplexers for setting wiper position. A new wiper position will
only engage pending a RST transition to the low state. The wiper position for the high-end terminals H0
and H1 will have data values FF (hex), while the low-end terminals will have data values 00 (hex).
STACKED CONFIGURATION
The potentiometers of the DS1867 can be connected in series as shown in Figure 4. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as RTOT/256 (per potentiometer); where
RTOT is equal to the device resistance value. The wiper output for the combined stacked potentiometer will
be taken at the Sout pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or
potentiometer-1 (W1). The potentiometer wiper selected at the Sout output is governed by the setting of
www.DataSheet4U.comthe stack select bit (bit-0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed
output, Sout, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed
output, Sout, will be that of the potentiometer-1 wiper.
STACKED CONFIGURATION Figure 4
CASCADE OPERATION
A feature of the DS1867 is the ability to control multiple devices from a single processor. Multiple
DS1867s can be linked or daisy-chained as shown in Figure 5. As a data bit is entered into the I/O shift
register of the DS1867 it will appear at the Cout output after a maximum delay of 70 nanoseconds.
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DS1867
ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C;VCC= 5V ± 10%)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
End-to-End Resistor Tolerance
Absolute Linearity
Relative Linearity
-20
±0.75
±0.30
+20
%
LSB
LSB
17
4
5
-3 dB Cutoff Frequency
fCUTOFF
Hz 7
Noise Figure
120 dB/(Hz)1/2
Temperature Coefficient
750 ppm/°C
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
MIN
(TA = 25°C)
TYP MAX UNITS NOTES
5 pF 3
7 pF 3
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL MIN
(-40°C to +85°C; VCC= 5V ± 10%)
TYP MAX UNITS NOTES
www.DataSheet4U.comCLK Frequency
fCLK DC
10 MHz
Width of CLK Pulse
tCH 50
ns
Data Setup Time
tDC 30
ns
Data Hold Time
tCDH
10
ns
Propagation Delay Time
Low to High Level
Clock to Output
tPLH
70 ns
15
15
15
15
13,15
Propagation Delay Time
High to Low Level
Clock to Output
RST High to Clock Input High
tPHL
tCC
50
70 ns 13,15
ns 15
RST Low to Clock Input High
tHLT
50
ns 15
CLK Rise Time
tCR
50 ns 15
RST Inactive
tRLT 200
ns 15
NONVOLATILE MEMORY CHARACTERISTICS
(-40°C to +85°C; VCC= 5V ± 10%)
PARAMETER
SYMBOL MIN
TYP MAX UNITS NOTES
Writes
25000
16
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS1867.PDF ] | |
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