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M6MGT331S8BKT fiches techniques PDF

Renesas - CMOS SRAM

Numéro de référence M6MGT331S8BKT
Description CMOS SRAM
Fabricant Renesas 
Logo Renesas 





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M6MGT331S8BKT fiche technique
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Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T331S8BKT
33,554,432-BIT (2,097,152 - WORD BY 16-BIT /4,194,304-WORD BY 8-BIT) CMOS
FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT /1,048,576-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Description
The M6MGB/T331S8BKT is a Stacked micro Multi Chip
Package (S- µMCP) that contents 32M-bit Flash memory
and 8M-bit Static RAM in a 52-pin TSOP for lead free use.
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152
words, , single power supply and high performance non-
volatile memory fabricated by CMOS technology for the
peripheral circuit and DINOR (Divided bit-line NOR IV)
architecture for the memory cell. All memory blocks are
locked and can not be programmed or erased, when F-WP#
is low. Using Software Lock Release function, program or
erase operation can be executed.
8M-bit SRAM is a 1,048,576 bytes / 524,288 words
asynchronous SRAM fabricated by CMOS technology for the
peripheral circuit .
The M6MGB/T331S8BKT is suitable for a high
performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small
power dissipation
Features
Access Time Flash
70ns (Max.)
SRAM
85ns (Max.)
Supply Voltage
VCC=2.7 ~ 3.0V
Ambient Temperature
Ta=-40 ~ 85 °C
Package
52pin TSOP(Type-II),
Application
Lead pitch 0.4mm
Outer-lead finishing:Sn-Cu
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
A15 1
52 A16
A14 2
51 BYTE#
A13 3
A12 4
www.DataSheet4U.comA11 5
50 S-UB#
49 GND
48 S-LB#
A10 6
47 DQ15/A-1
A9 7
46 DQ7
A8 8
45 DQ14
A19 9
44 DQ6
S-CE1#
10
43 DQ13
WE#
11
42 DQ5
F-RP#
12
41 DQ12
F-WP#
S-VCC
13
14
M6MGB/T331S8BKT
40
39
DQ4
F-VCC
S-CE2
15
38 DQ11
DU 16
37 DQ3
A20 17
36 DQ10
A18 18
35 DQ2
A17 19
34 DQ9
A7 20
33 DQ1
A6 21
32 DQ8
A5 22
31 DQ0
A4 23
30 OE#
A3 24
29 GND
A2 25
28 F-CE#
A1 26
27 A0
10.49 mm
Outline
52PTJ-A
F-VCC
S-VCC
GND
A-1 - A18
A19 - A20
DQ0 - DQ15
F-CE#
S-CE1#
S-CE2
OE#
WE#
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable1
:SRAM Chip Enable2
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
F-WP#
F-RP#
BYTE#
S-LB#
S-UB#
DU
:Flash Write protect
:Flash Reset Power Down
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
:Do not use
1 Rev.0.1.48a_bebz
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