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PDF M6MGT331S4BKT Data sheet ( Hoja de datos )
| Número de pieza | M6MGT331S4BKT | |
| Descripción | CMOS SRAM | |
| Fabricantes | Renesas | |
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Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T331S4BKT
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Description
The M6MGB/T331S4BKT is a Stacked micro Multi Chip
Package (S- µMCP) that contents 32M-bit Flash memory and
4M-bit Static RAM in a 52-pin TSOP for lead free use.
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words,
3.3V-only, and high performance non-volatile memory
fabricated by CMOS technology for the peripheral circuit and
DINOR (Divided bit-line NOR) architecture for the memory cell.
4M-bit SRAM is a 524,288 bytes / 262,144 words
asynchronous SRAM fabricated by silicon-gate CMOS
technology.
M6MGB/T331S4BKT is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight.
M6MGB/T331S4BKT provides for Software Lock Release
function. Usually, all memory blocks are locked and can not
be programmed or erased, when F-WP# is low. Using
Software Lock Release function, program or erase operation
can be executed.
Features
Access Time Flash
70ns (Max.)
SRAM
70ns (Max.)
Supply Voltage
VCC=2.7 ~ 3.0V
Ambient Temperature
Ta=-40 ~ 85 °C
Package
52pin TSOP(Type-II),
Application
Lead pitch 0.4mm
Outer-lead finishing:Sn-Cu
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
A15 1
52 A16
A14 2
51 BYTE#
A13 3
50 S-UB#
A12 4
49 GND
A11 5
48 S-LB#
A10 6
A9 7
www.DataSheet4U.comA8 8
47 DQ15/A-1
46 DQ7
45 DQ14
A19 9
44 DQ6
S-CE1#
10
43 DQ13
WE#
11
42 DQ5
F-RP#
12
41 DQ12
F-WP#
S-VCC
13
14
M6MGB/T331S4BKT
40
39
DQ4
F-VCC
S-CE2
15
38 DQ11
DU 16
37 DQ3
A20 17
36 DQ10
A18 18
35 DQ2
A17 19
34 DQ9
A7 20
33 DQ1
A6 21
32 DQ8
A5 22
31 DQ0
A4 23
30 OE#
A3 24
29 GND
A2 25
28 F-CE#
A1 26
27 A0
10.49 mm
Outline 52PTJ-A
F-VCC
S-VCC
GND
A-1-A17
A18-A20
DQ0-DQ15
F-CE#
S-CE#,S-CE2
OE#
WE#
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
F-WP#
F-RP#
F-RY/BY#
BYTE#
S-LB#
S-UB#
DU
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready/Busy
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
:Do not use
1 Rev.0.1_48a_beez
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