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PDF HY27UA161G1M Data sheet ( Hoja de datos )
| Número de pieza | HY27UA161G1M | |
| Descripción | (HY27SAxxx) 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
No. History
0.0 1) Initial Draft
0.1 1) Add 1.8V Operation Product to Data sheet
1) Change AC Characteristics
0.2 - tWP(25ns->40ns), tWC(50ns->60ns),
- tRP(30ns->40ns), tRC(50ns->60ns),
- tREADID(35ns->45ns)
1) Add Errata (3V Product)
Draft Date Remark
Nov. 28. 2003 Preliminary
Mar. 11. 2004 Preliminary
Apr. 29. 2004 Preliminary
tWH tREH
Specification 15 15
Relaxed value 20 20
0.3 May. 14. 2004 Preliminary
2) Add Applicaiton Note
Reset command must be issued when the controller writes data to
another 512Mb.(i.e. When A26 is changed during program.)
3) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page22)
4) Add the description of System Interface Using /CE don’t care (Page37)
1) Delete Errata
2) Change Characteristics
tCRY
0.4 Before 60 + tr
After
70 + tr
tREA@ID Read
35
45
Jun. 01. 2004 Preliminary
3) Delete Cache Program
1) Change TSOP1, WSOP1, FBGA package dimension
0.5 2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Oct. 2004
1
1 page  
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1 48
11 23
NAND Flash
(x8)
33 76
24 25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1 48
11 23
NAND Flash
(x16)
33 76
24 25
Figure 3. 48-TSOP1 Contactions, x8(x16) Device
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
Vcc
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
NC 1
NC
48
DU
NC
NC
NC
RB
RE
CE
DU NAND Flash
NC
Vcc
12
WSOP1
37
Vss 13
(x8)
36
NC
DU
CLE
ALE
WE
WP
NC
NC
DU
NC
NC 24
25
NC
NC
DU
NC
I/O7
I/O6
I/O5
I/O4
NC
DU
NC
Vcc
Vss
NC
DU
NC
I/O3
I/O2
I/O1
I/O0
NC
DU
NC
NC
Figure 4. 48-WSOP1 Contactions, x8 Device
Rev 0.5 / Oct. 2004
5
5 Page 
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Table 2. Bus Operation
BUS Operation
Command Input
Address Input
Data Input
Data Output
Write Protect
Standby
CE
VIL
VIL
VIL
VIL
X
VIH
ALE
VIL
VIH
VIL
VIL
X
X
CLE RE WE WP
VIH
VIH
Rising
X(2)
VIL
VIH Rising
X
VIL
VIH Rising
X
VIL
Falling
VIH
X
X X X VIL
X X XX
I/O0 - I/O7
Command
Address
Data Input
Data Output
X
X
I/O8 - I/O15(1)
X
X
Data Input
Data Output
X
X
Note : (1) Only for x16 devices.
(2) WP must be VIH when issuing a program or erase command.
Table 3: Address Insertion, x8 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O7
A7
A16
A24
VIL
I/O6
A6
A15
A23
VIL
I/O5
A5
A14
A22
VIL
I/O4
A4
A13
A21
VIL
I/O3
A3
A12
A20
VIL
I/O2
A2
A11
A19
VIL
I/O1
A1
A10
A18
A26
I/O0
A0
A9
A17
A25
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any additional address input cycles will be ignored with tALS > 0ns.
Table4: Address Insertion, x16 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O8-I/
O15
X
X
X
VIL
I/O7
A7
A16
A24
VIL
I/O6
A6
A15
A23
VIL
I/O5
A5
A14
A22
VIL
I/O4
A4
A13
A21
VIL
Note: (1). A8 is Don't Care in x16 devices.
(2). Any additional address input cycles will be ignored with tALS > 0ns.
(3). A1 is the Least Significant Address for x16 devices.
(4). The 01h Command is not used in x16 devices.
I/O3
A3
A12
A20
VIL
I/O2
A2
A11
A19
VIL
I/O1
A1
A10
A18
A26
I/O0
A0
A9
A17
A25
Rev 0.5 / Oct. 2004
11
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