PDF ICS9FG104 Data sheet ( Hoja de datos )

Número de pieza	ICS9FG104
Descripción	Programmable FTG for Differential P4TM CPU
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG104 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks Recommended Application: Pin Configuration Frequency Timing Generator for Differential CPU & SATA clocks Features: • Generates common CPU frequencies from 14.318 MHz or 25 MHz • Crystal or reference input • 4 - 0.7V current-mode differential output pairs XIN/CLKIN X2 VDD GND REFOUT FS2 DIF_3 1 2 3 4 5 6 7 28 VDDA 27 GNDA 26 IREF 25 FS0 24 FS1 23 DIF_0 22 DIF_0# • Supports Serial-ATA at 100 MHz DIF_3# 8 21 VDD • Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread VDD 9 GND 10 20 GND 19 DIF_1 • Unused inputs may be disabled in either driven or Hi- Z state for power management. DIF_2 11 DIF_2# 12 18 DIF_1# 17 SEL14M_25M# • M/N Programming SDATA 13 16 SPREAD SCLK 14 15 DIF_STOP# Key Specifications: • Output cycle-to-cycle jitter < 50 ps 28-pin SSOP/TSSOP • Output to output skew < 35 ps • +/-300 ppm frequency accuracy on output clocks • +/- 150 ppm frequency accuracy @ 100 MHz outputs Frequency Select Table SEL14M_25M# (FS3) FS2 FS1 FS0 OUTPUT(MHz) 0 000 100.00 0 001 125.00 0 010 133.33 0 011 166.67 0 100 200.00 0 101 266.00 0 110 333.00 0 111 400.00 1 000 100.00 1 001 125.00 1 010 133.33 1 011 166.67 1 100 200.00 1 101 266.00 1 110 333.00 1 111 400.00 0839G—06/05/06 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG104 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Output Impedance Zo1 VO = Vx 3000 Voltage High Voltage Low VHigh VLow Statistical measurement on single ended signal using oscilloscope math function. 660 -150 Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Measurement on single ended signal using absolute value. -300 250 TYP MAX 850 150 1150 550 UNITS Ω mV mV mV Crossing Voltage (var) d-Vcross Crossing variation over all edges 140 mV Long Accuracy ppm see Tperiod min-max values -300 300 ppm 400MHz nominal 2.4993 2.5008 ns 400MHz spread 2.4993 2.5133 ns 333.33MHz nominal 2.9991 3.0009 ns 333.33MHz spread 2.9991 3.016 ns 266.66MHz nominal 3.7489 3.7511 ns 266.66MHz spread 3.7489 3.77 ns Average period Tperiod 200MHz nominal 200MHz spread 4.9985 4.9985 5.0015 5.0266 ns ns 166.66MHz nominal 5.9982 6.0018 ns 166.66MHz spread 5.9982 6.0320 ns 133.33MHz nominal 7.4978 7.5023 ns 133.33MHz spread 7.4978 5.4000 ns 100.00MHz nominal 9.9970 10.0030 ns 100.00MHz spread 9.9970 10.0533 ns 400MHz nominal/spread 2.4143 ns 333.33MHz nominal/spread 2.9141 ns 266.66MHz nominal/spread 3.6639 ns Absolute min period Tabsmin 200MHz nominal/spread 4.8735 ns 166.66MHz nominal/spread 5.8732 ns 133.33MHz nominal/spread 7.3728 ns 100.00MHz nominal/spread 9.8720 ns Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps Rise Time Variation d-tr 125 ps Fall Time Variation d-tf 125 ps Duty Cycle dt3 Measured Differentially 45 55 % Skew, output to output Jitter, PCI-e SRC phase tsk3 tjPCI-ephase14 VT = 50% 22MHz/1.5MHz/1.5MHz/10ns, 14.31818 MHz REF Clock 35 ps 42 ps Jitter, PCI-e SRC phase tjPCI-ephase25 22MHz/1.5MHz/1.5MHz/10ns, 25 MHz REF Clock 39 ps Jitter, Cycle to cycle tjcyc-cyc Measured Differentially 1Guaranteed by design and characterization, not 100% tested in production. 50 ps 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz 3 Figures are for down spread. 4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 +/- 150 ppm for 100 MHz outputs NOTES 1 1 1 1 1 1 1 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 4 4 4 1 0839G—06/05/06 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG104 SMBus Table: PLL Frequency Control Register Byte 10 Pin # Name Control Function Bit 7 - PLL N Div8 N Divider Prog bit 8 Bit 6 - PLL N Div9 N Divider Prog bit 9 Bit 5 - PLL M Div5 Bit 4 - PLL M Div4 Bit 3 - PLL M Div3 M Divider Bit 2 - PLL M Div2 Programming Bit 1 - PLL M Div1 bit (5:0) Bit 0 - PLL M Div0 Type 0 1 PWD RW The decimal RW representation of M and N Divider in Byte 11 and RW 12 will configure the PLL RW VCO frequency. X X X X RW Default at power up = X RW latch-in or Byte 0 Rom RW table. VCO Frequency = 14.318 x X X RW [NDiv(9:0)+8] / [MDiv(5:0)+2] X SMBus Table: PLL Frequency Control Register Byte 11 Pin # Name Control Function Bit 7 - PLL N Div7 Bit 6 - PLL N Div6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - - - - - PLL N Div5 PLL N Div4 PLL N Div3 PLL N Div2 PLL N Div1 N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Bit 0 - PLL N Div0 Type 0 1 PWD RW The decimal RW representation of M and RW N Divider in Byte 11 and 12 will configure the PLL RW VCO frequency. RW Default at power up = X X X X X RW latch-in or Byte 0 Rom RW table. VCO Frequency = 14.318 x X X RW [NDiv(9:0)+8] / [MDiv(5:0)+2] X SMBus Table: PLL Spread Spectrum Control Register Byte 12 Pin # Name Control Function Bit 7 - PLL SSP7 Bit 6 - PLL SSP6 Bit 5 - PLL SSP5 Bit 4 - PLL SSP4 Spread Spectrum Bit 3 - PLL SSP3 Programming bit(7:0) Bit 2 - PLL SSP2 Bit 1 - PLL SSP1 Bit 0 - PLL SSP0 Type 0 1 RW RW RW These Spread RW Spectrum bits in Byte 13 and 14 will program RW the spread pecentage RW of PLL RW RW PWD X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 0 1 Bit 7 - Reserved Bit 6 - PLL SSP14 RW Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - - - - - PLL SSP13 PLL SSP12 PLL SSP11 PLL SSP10 PLL SSP9 RW These Spread Spread Spectrum Programming bit(14:8) RW RW RW Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL RW Bit 0 - PLL SSP8 RW PWD 0 X X X X X X X 0839G—06/05/06 11 11 Page

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