PDF A1020B-xxxx Data sheet ( Hoja de datos )

Número de pieza	A1020B-xxxx
Descripción	FPGAs
Fabricantes	Actel
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No Preview Available ! www.DataSheet4U.com v3.0 RadTolerant FPGAs Features General Characteristics • Tested Total Ionizing Dose (TID) Survivability Level • No Single Event Latch-up Below a Minimum LET Threshold of 80 MeV-cm2/mg for All RT Devices • Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin Ceramic Quad Flat Pack • Offered as Class B and E-Flow (Actel Space Level Flow) • QML Certified Devices • 100% Military Temperature Tested (–55°C to +125°C) High Density and Performance • 4,000 to 20,000 Logic Equivalent Gates • 2,000 to 10,000 ASIC Equivalent Gates • Up to 85 MHz Internal Performance • Up to 60 MHz System Performance • Up to 228 User I/Os • Up to Four Fast, Low-Skew Clock Networks Easy Logic Integration • Non-Volatile, User Programmable • Pin-Compatible Commercial Devices Available for Prototyping • Highly Predictable Performance with 100% Automatic Place and Route • 100% Resource Utilization with 100% Pin-Locking • Secure Programming Technology Prevents Reverse Engineering and Design Theft • Permanently Programmed for Operation on Power-Up • Unique In-System Diagnostic and Verification Capability with Silicon Explorer General Description Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (FITs), corresponding to a useful life of more than 40 years. Actel FPGAs are production-proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an out-going defect level of only 122 ppm (further reliability data is available in the Actel Device Reliability Report at http://www.actel.com/hirel). Additionally, the programmable architecture of these devices offers high performance, design flexibility, and fast and inexpensive prototyping—all without the expense of test vectors, NRE charges, long lead times, and schedule and cost penalties for design refinements. Product Family Profile Device Capacity System Gates Logic Gates ASIC Equivalent Gates PLD Equivalent Gates mTTL Equivalent Package o20-Pin PAL Equivalent Packages .cLogic Modules US-Modules t4C-Modules eUser I/Os (Maximum) hePerformance SSystem Speed (Maximum) taPackages (by Pin Count) a CQFP w.D January 2000 ww © 2000 Actel Corporation RT1020 6,000 4,000 2,000 5,000 50 20 547 N/A 547 69 20 MHz 84 RT1280A 24,000 16,000 8.000 20,000 200 80 1,232 624 608 140 40 MHz 172 RT1425A 7,500 5,000 2,500 6,250 60 25 310 160 150 100 60 MHz 132 RT1460A 18,000 12,000 6,000 15.000 150 60 848 432 416 168 60 MHz 196 RT14100A 30,000 20,000 10,000 25,000 250 100 1,377 697 680 228 60 MHz 256 1 1 page www.DataSheet4U.com RadTolerant FPGAs RadTolerant Architecture The Actel architecture is composed of fine-grained logic modules that produce fast, efficient logic designs. All devices are composed of logic modules, routing resources, clock networks, and I/O modules which are the building blocks for fast logic designs. Logic Modules These RadTolerant devices contain two types of logic modules, combinatorial (C-modules) and sequential (S-modules). RT1020 and A1020B devices contain only C-modules. The C-module, shown in Figure 1, implements the following function: Y=!S1!S0D00+!S1S0D01+S1!S0D10+S1S0D11 where: S0=A0B0 S1=A1+B1 The S-module, shown in Figure 2, is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-type A0 B0 A1 B1 S0 D00 D00 D10 D11 S1 Y Figure 1 • C-Module Implementation flip-flop or a transparent latch. To increase flexibility, the S-module register can be by-passed so it implements purely combinatorial logic. Flip-flops can also be created using two C-modules. The SEU characteristics differ between an S-module flip-flop and a flip-flop created using two C-modules. For details see the Design Techniques for RadHard Field Programmable Gate Arrays application note at http://www.actel.com/hirel. D00 D01 YD Q OUT D10 D11 S0 S1 CLR D00 D01 YD Q OUT D10 D11 S0 GATE S1 Up to 7-Input Function Plus D-Type Flip-Flop with Clear D0 mD1 .coS Y DQ GATE CLR OUT heet4UUp to 4-Input Function Plus Latch with Clear www.DataSFigure 2 • S-Module Implementation Up to 7-Input Function Plus Latch D00 D01 Y OUT D10 D11 S0 S1 Up to 8-Input Function (Same as C-Module) 5 5 Page www.DataSheet4U.com RadTolerant FPGAs Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a CQFP 172-pin package at military temperature is as follows: M------a--x----.---j-u---n---c---t--i-o---n-----t-e---m-----p---.---(--°--C----)----–----M-----a---x---.---m-----i-l--i--t-a---r--y-----t-e---m-----p---. = 1---5---0---°---C-----–-----1---2---5---°--C--- = 1.0W θj a ( °C/W ) 25°C/W Package Type Ceramic Quad Flat Pack Pin Count 84 132 172 196 256 θjc 7.8 7.2 6.8 6.4 6.2 θja Still Air 40 35 25 23 20 θja 300 ft/min 30 25 20 15 10 Units °C/W °C/W °C/W °C/W °C/W Power Dissipation General Power Equation P = [ICCstandby + ICCactive] VCC + IOL * VOL * N + IOH * (VCC – VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power dissipation can be machieved. .coThe power due to standby current is typically a small Ucomponent of the overall power. Standby power is calculated t4below for commercial, worst-case conditions. eeICC www.DataSh 2mA VCC 5.25V Power 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving HIGH or LOW and on the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving LOW, and 140 mW with all outputs driving HIGH. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by Equation 1: Power (uW) = CEQ * VCC2 * F (1) where: CEQ = Equivalent capacitance in pF VCC = Power supply in volts (V) F = Switching frequency in MHz 11 11 Page

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