PDF ICS527-01 Data sheet ( Hoja de datos )

Número de pieza	ICS527-01
Descripción	User Configurable Zero Delay Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com ICS527-01 Clock Slicer™ User Configurable Zero Delay Buffer Description The ICS527-01 Clock Slicer™ is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates the rising clock edges that are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-01 aligns rising edges on ICLK and FBIN at a ratio determined by the reference and feedback dividers. For configurable clocks that do not require zero delay, use the ICS525. Block Diagram Features • Packaged as 28 pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • User determines the output frequency - no software needed • Slices frequency or period • SYNC pulse output indicates aligned edges • Input clock frequency of 600 kHz - 200 MHz • Output clock frequencies up to 160 MHz • Very low jitter • Duty cycle of 45/55 up to 160 MHz • Operating voltage of 3.3 V (±10%) • Pin selectable double drive strength • Multiple outputs available when combined with Buffalo clock drivers • Zero input to output skew • Industrial temperature version available • Advanced, low power CMOS process R6:R0 S1:S0 2XDRIVE ICLK FBIN 7 Reference Divide Feedback Divide 7 PDTS 2 PLL PDTS SYNC ÷2 1 0 CLK1 CLK2 PDTS OECLK2 DIV2 F6:F0 www.DataSheet4U.com External feedback from CLK1 or CLK2 (not both). MDS 527-01 B 1 Revision 020801 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com 1 page www.DataSheet4U.com ICS527-01 Clock Slicer™ User Configurable Zero Delay Buffer Typical Example The following connection diagram shows the implementation of the example from the previous section. This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x output drive is selected. VDD 0.01 µF 40 MHz R5 R6 DIV2 S0 S1 VDD ICLK FBIN GND OECLK2 2XDRIVE F0 F1 F2 R4 R3 R2 R1 R0 VDD CLK1 CLK2 GND PDTS F6 F5 F4 F3 0.01 µF 33Ω 33Ω 50 MHz SYNC Note that the feedback is done AFTER the series termination resistor. This will give the following waveforms: 40 MHz ICLK 50 MHz CLK1 SYNC CLK2 www.DataSheet4U.com MDS 527-01 B 5 Revision 020801 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ICS527-01	User Configurable Zero Delay Buffer	Integrated Circuit Systems
ICS527-02	Clock Slicer User Configurable PECL Input Zero Delay Buffer	Integrated Circuit Systems
ICS527-03	Clock Slicer User Configurable PECL Output Zero Delay Buffer	Integrated Circuit Systems
ICS527-04	Clock Slicer User Configurable PECL input Zero Delay Buffer	Integrated Circuit Systems

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