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PDF ICS525R-07 Data sheet ( Hoja de datos )
| Número de pieza | ICS525R-07 | |
| Descripción | (ICS525R-07/08) LVCMOS User Configurable Clock | |
| Fabricantes | Integrated Circuit Systems | |
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PRELIMINARY INFORMATION ICS525-07/08
LVCMOS User Configurable Clock
Description
The ICS525-07/08 are the most flexible way to
generate a high-quality clock output from an
inexpensive crystal or clock input at low supply
voltages. The user can configure the device to produce
nearly any output frequency from any input frequency
by grounding or floating the select pins or by driving or
hard wiring the select pins high or low. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked.
For similar capability with a serial interface, use the
ICS307.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew is not defined nor guaranteed.
Features
• Packaged as 28-pin SSOP (150 mil body)
• Available in Pb (lead) free package
• User determines the output frequency by setting all
internal dividers
• Eliminates need for custom oscillators
• Low voltage operation
• Pull-ups on all select inputs
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Compensated loop bandwidth
• Enhanced low frequency operation (-08 version)
• Low jitter
• Duty cycle of 45/55 up to 200 MHz
• Operating voltage of 1.8 V to 2.5 V
• Ideal for oscillator replacement
• Available in commercial and industrial temperature
ranges
Block Diagram
PD
X1/ICLK
Crystal or clock
input X2
OOppttiioonnaall ccrryyssttaall ccaappaacciittoorrss
Crystal
Oscillator
Reference
Divider
2 VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VVCO
DDiivviiddeerr
VCO
Output
Divider
RR CCoonnffiigguurraattiioonn PPiinnss
VV CCoonnffiigguurraattiioonn PPiinnss
22 GGNNDD
SS CCoonnffiigguurraattiioonn PPiinnss
REF
CLK
www.DataSheet4U.com
MDS 525-07/08 A
1
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
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PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-07/08 require two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Configuring the Frequency
The ICS525-07/08 output frequency is determined by
its internal dividers according to this equation:
fOUT
=
V
R
*
*
fIN
OD
V is the feedback divider and can be 8, 9, 10, 12...519
(not 11).
For the ICS525-07, R is the reference divider and can
be 2, 3, 4...129.
For the ICS525-08, R can be 1, 2...64.
For the ICS525-07, OD can be 1, 2, 3, 4, 5, 7, 12, or 16.
For the ICS525-08, OD can be 2, 3, 4, 5, 7, 8, 9, 10, 11,
13, 14, 15, 17, 19, 48, or 128.
The VCO must be kept in its operating range according
to this equation:
50MHz <
V * fIN
R
< 400MHz
The phase detector must be kept in its operating range
according to this equation:
250kHz <
fIN
R
Optimum values for V, R, and OD are found iteratively
by applying the above equations. Choosing a smaller
value of R will give better jitter. A calculator program is
available on the ICS website to automate the process.
After determining V, R, and OD, convert them to the pin
address.
V8...0 = binary(V - 8)
Example: V = 17, V8...0 = 000001001
For the ICS525-07, R6...0 = binary(R - 2)
Example: R = 15, R6...0 = 0001101
For the ICS525-08, R5...0 - binary(R - 2)
Example: R = 15, R5...0 = 001101
S2...0 or S3...0 is configured according to the tables on
page 4.
All of the configuration pins have on-chip pull-up
resistors, so pins can be floated to generate a “1”, or
tied to ground for a “0”. They can also be driven directly
by logic signals.
Output Termination
The output driver impedance is approximately 17
ohms. Use a 33 ohm series termination resistor on
each output to match a 50 ohm trace.
Reference Source
The initial accuracy and temperature stability of the
output frequency is determined by the reference
frequency source, the crystal, or the input clock. The
PLL will track the input frequency, so if the crystal is
running at +5 ppm the CLK frequency will also be +5
ppm. A low amplitude sinusoidal reference (such as the
1 V p-p signal from a TCXO) can be used by the AC
coupling it to the X1 pin with a 0.1 µF capacitor. The X1
pin is self-biasing.
www.DataSheet4U.com
MDS 525-07/08 A
5
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page | ||
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