PDF NT5SV4M16DT Data sheet ( Hoja de datos )

Número de pieza	NT5SV4M16DT
Descripción	(NT5SVxxMxxDT) 64Mb Synchronous DRAM
Fabricantes	NANYA
Logotipo
Hay una vista previa y un enlace de descarga de NT5SV4M16DT (archivo pdf) en la parte inferior de esta página. Total 21 Páginas
No Preview Available ! www.DataSheet4U.com NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Features • High Performance: -6K -7K fCK Clock Frequency 166 133 143 133 tCK Clock Cycle 6 7.5 7 7.5 CL CAS Latency CL=3 CL=2 CL=3 CL=2 tAC Clock Access Time1 --- — --- — tAC Clock Access Time2 5.4 5.4 5.4 5.4 -7 143 7 CL=3 — 5.4 Units MHz ns CKs ns ns 1. Terminated load. See AC Characteristics on page 16. 2. Unterminated load. See AC Characteristics on page 16. • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by BS0/BS1 (Bank Select) • Programmable CAS Latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8, Full page • Programmable Wrap: Sequential or Interleave • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (x4, x8) • Dual Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • Standard Power operation • 4096 refresh cycles/64ms • Random Column Address every CK (1-N Rule) • Single 3.3V ± 0.3V Power Supply • LVTTL compatible • Package: 54-pin 400 mil TSOP-Type II Description The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT are four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 200MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/out- put (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are exam- ined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combina- tions of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional RAS/CAS mul- tiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (BS0, BS1) are strobed with RAS. Eleven column addresses (A0-A9) plus bank select addresses and A10 are strobed with CAS. Column address A9 is dropped on the x8 device, and column addresses A8 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BS0, BS1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache oper- ation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gap- less data rate of up to 200MHz is possible depending on burst length, CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR) and Self Refresh operation are supported. www.DataSheet4U.com REV 1.1 10/01 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1 page www.DataSheet4U.com NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Block Diagram CKE CKE Buffer CLK CLK Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 BS0 BS1 A10 Column Decoder Cell Array Memory Bank 0 Sense Amplifiers Column Decoder Cell Array Memory Bank 1 Sense Amplifiers DQ0 DQX CS RAS CAS WE Column Decoder Cell Array Memory Bank 2 Sense Amplifiers DQM Column Decoder Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15). www.DataSheet4U.com REV 1.1 10/01 5 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 5 Page www.DataSheet4U.com NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Current State Truth Table (Part 2 of 3)(See note 1) Command Current State CS RAS CAS WE BS0,BS1 A11 - A0 Description Action Notes Read with Auto Pre- charge LLLL L L LH LLHL L LHH LHL L LHLH L HH L L HHH HXXX OP Code Mode Register Set X X Auto or Self Refresh BS X Precharge BS Row Address Bank Activate BS Column Write BS Column Read X X Burst Termination X X No Operation X X Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 4 4 4 4 LLLL L L LH OP Code XX Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL LLHL L LHH Write with Auto Precharge L H L L LHLH L HH L L HHH HXXX LLLL L L LH LLHL L LHH BS X Precharge BS Row Address Bank Activate BS Column Write BS Column Read X X Burst Termination X X No Operation X X Device Deselect OP Code Mode Register Set X X Auto or Self Refresh BS X Precharge BS Row Address Bank Activate ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL 4 4 4 4 4 Precharging L H L L LHLH BS BS Column Column Write Read ILLEGAL ILLEGAL 4 4 Row Activating L HH L L HHH HXXX LLLL L L LH LLHL L LHH LHL L LHLH L HH L L HHH HXXX X X Burst Termination X X No Operation X X Device Deselect OP Code Mode Register Set X X Auto or Self Refresh BS X Precharge BS Row Address Bank Activate BS Column Write BS Column Read X X Burst Termination X X No Operation X X Device Deselect No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 4, 10 4 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer- enced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. www.DataSheet4U.com REV 1.1 10/01 11 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 11 Page

Páginas	Total 21 Páginas
PDF Descargar	[ Datasheet NT5SV4M16DT.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
NT5SV4M16DT	(NT5SVxxMxxDT) 64Mb Synchronous DRAM	NANYA

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar