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PDF KS8620 Data sheet ( Hoja de datos )
| Número de pieza | KS8620 | |
| Descripción | 1 Chip CODEC for Digital Answering phone | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KS8620
1 Chip CODEC for Digital Answering phone
INTRODUCTION
The KS8620 consists of on-chip PCM encoders, decoders
16-DIP-300
(PCM CODECs) and PCM line filter. This device
provide all the functions required to interface a full-
duplex voice telephone circuit, digital answering phone.
This device is designed to perform the transmit encoding
and receive decoding as well as the transmit and receive
filtering function in PCM system. Also it is intended to be
16-SOP-BD300 - SG
used at the analog termination of a PCM line / trunk.
This device provide the Band pass filtering of the analog
signals prior to encoding and after decoding. This
combination device performs the encoding and decoding
of voice and call progress tones as well as the signaling
and supervision information.
ORDERING INFORMATION
Device
Package
Operating Temperature
FEATURES
KS8620N
KS8620D
16-DIP-300
16-SOP- BD300 - SG
0oC ~ + 70oC
• Complete CODEC and filtering system
• Encoding / Decoding : 8 bits µ-law PCM
• On-chip auto zero, sample and hold,
and precision voltage references
• Low power dissipation : 60mW ( operating )
3mW ( standby )
• + 5V operation
• TTL or CMOS compatible
• Automatic power down
PIN CONFIGURATION
V BB 1
GNDA 2
VF RO 3
V CC 4
FS R 5
DR 6
BCLKR/CLKSEL 7
MCLK
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R/PDN
8
KS8620
16 VFIXI+
15 VFXI-
14 GSX
13 TSX
12 FSX
11 DX
10 BCLKX
9 MCLKX
1 page  
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KS8620
1 Chip CODEC for Digital Answering phone
TIMING CHARACTERISTICS
(Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V )
Characteristic
System
Test Conditions
Min Typ
Max Unit
Depends on the device used
1.536
MHz
Frequency of Master Clock
fMCK and the BCLKR /CLKSEL pin.
1.544
MCLKx and MCLKR
2.048
Rise time of Bit Clock
tR(BCK) tPB = 488ns
50 nS
Fall Time of Bit Clock
tF(BCK) tPB = 488ns
50 nS
Hold Time for Bit Clock
tH(LFS) Long Frame only
0 nS
low to Frame sync
Hold Time for Bit Clock
tH(HFS) Short Frame only
0 nS
High to Frame sync
Set-up Time from Frame
tSU(FBCL) Long Frame only
80 nS
sync to Bit Clock low
Delay time from BCLKx
tD(HDV) Load = 150pF + 2 LSTTL loads
0
180 nS
High to data valid
Delay time to /TSx low
tD(/TSXL) Load = 150pF + 2 LSTTL loads
140 nS
Delay time from BCLKx
tD(LDD)
50 165 nS
low to data output disable
Delay Time to valid data
tD(VD) CL = 0 pF to 150 pF
20 165 nS
from FSx or BCLKx.
Whichever comes later.
Set-up Time from DR valid
tSU(DRBL)
50 nS
to BCLK x/R low
Hold time from BCLK x/R
tH(BLDR)
50 nS
low to DR invalid
Set-up time from FS x/R to tSU(FBLS) Short Frame sync pulse ( 1 or 2 bit
50
nS
BCLK x/R low
clock periods long ) : note1
Width of master clock High tW(MCKH) MCLKx and MCLKR
160
nS
Width of master clock Low tW(MCKL) MCLKx and MCLKR
160
nS
Rise Time of Master clock tR(MCK) MCLKx and MCLKR
50 nS
Fall Time of Master clock
tF(MCK) MCLKx and MCLKR
50 nS
Set-up time from BCLKx High tSU(BHMF) 1`st bit clock after the leading
50
nS
( FSx in Long Frame Sync
edge of FSx
mode ) to MCLKx falling edge
Period of Bit Clock
tCK
485 488 15,725 nS
Width of Bit clock High
tW(BCKH) VIH = 2.2V
160 nS
Width of Bit clock Low
tW(BCKL) VIL = 0.6V
160 nS
Hold time from BCLK x/R
tH(BLFL) Short Frame sync pulse ( 1 or 2 bit
to FwSwx/wR .lDowataSheet4U.com
clock periods long ) : note1
100
nS
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KS8620.PDF ] | |
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