DataSheet.es    


PDF ICS94209 Data sheet ( Hoja de datos )

Número de pieza ICS94209
Descripción Programmable Frequency Generator & Integrated Buffers
Fabricantes Integrated Circuit Systems　
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS94209 (archivo pdf) en la parte inferior de esta página.


Total 19 Páginas

No Preview Available ! ICS94209 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS94209
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Recommended Application:
Single chip clock solution 630S chipset.
Output Features:
• 3 - CPU @ 2.5V
• 13 - SDRAM @ 3.3V
• 6- PCI @3.3V,
• 2 - AGP @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 2- REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable SDRAM and CPU skew.
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps (except SDRAM12)
• PCI - PCI: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
1*(AGPSEL)REF0
1*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDL
47 CPUCLK0
46 CPUCLK1
45 CPUCLK2
44 GND
43 VDDSDR
42 SDRAM0
41 SDRAM1
40 SDRAM2
39 GND
38 SDRAM3
37 SDRAM4
36 SDRAM5
35 VDDSDR
34 SDRAM6
33 SDRAM7
32 GND
31 SDRAM8/PD#
30 SDRAM9/SDRAM_STOP#
29 GND
28 SDRAM10/PCI_STOP#
27 SDRAM11/CPU_STOP#
26 SDRAM12
25 VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
PLL2
X1 XTAL
X2 OSC
/2
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
SDRAM
DIVDER
SDATA
SCLK
FS(3:0)
Control
Logic
PCI
DIVDER
PD#
PCI_STOP#
AGP
DIVDER
CPU_STOP#
Config.
SwDRwAMw_ST.ODP#ataShReege. t4U.com
MODE
AGP_SEL
Stop
Stop
Functionality
48MHz
24_48MHz
REF(1:0)
2
3 CPUCLK (2:0)
SDRAM (12:0)
13
5 PCICLK (4:0)
PCICLK_F
AGP (1:0)
2
FS3 FS2 FS1 FS0 CPU SDRAM
0 0 0 0 66.67 66.67
0 0 0 1 100.00 100.00
0 0 1 0 166.67 166.67
0 0 1 1 133.33 133.33
0 1 0 0 66.67 100.00
0 1 0 1 100.00 66.67
0 1 1 0 100.00 133.33
0 1 1 1 133.33 100.00
1 0 0 0 112.00 112.00
1 0 0 1 124.00 124.00
1 0 1 0 138.00 138.00
1 0 1 1 150.00 150.00
1 1 0 0 66.67 133.33
1 1 0 1 100.00 150.00
1 1 1 0 150.00 100.00
1 1 1 1 160.00 120.00
P CICLK
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.60
31.00
34.50
30.00
33.33
30.00
30.00
30.00
AGP
SEL = 0
66.67
66.67
66.66
66.67
66.67
66.67
66.67
66.67
67.20
62.00
69.00
60.00
66.67
60.00
60.00
60.00
AGP
SEL = 1
50.00
50.00
55.56
50.00
50.00
50.00
50.00
50.00
56.00
46.50
51.75
50.00
50.00
50.00
50.00
48.00
94209 RevA - 04/27/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

1 page




ICS94209 pdf
www.DataSheet4U.com
ICS94209
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 2,3 0 REF strength 0=1X, 1=2X
Bit6 45
CPUCLK2 - Stop - Control
0 0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit5 -
X AGPSEL (Readback)
Bit4 -
X MODE (Readback)
Bit3 -
X CPU_STOP# (Readback)
Bit2 -
X PCI_STOP# (Readback)
Bit1 -
X SDRAM_STOP# (Readback)
Bit0 -
AGP Speed Toggle
0 0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
1 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
1 Reserved
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
Byte 9: Watchdog Timer Count Register
Bit PWD
Description
Bit 7 0
Bit 6 0 The decimal representation of these
Bit 5 0 8 bits correspond to 290ms or 1ms
Bit 4
Bit 3
1
0
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
Bit 2 0 at power up is 16X 290ms = 4.6
Bit 1 0 seconds.
Bit 0 0
www.DataSheet4U.com
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Third party brands and names are the property of their respective owners.
5

5 Page





ICS94209 arduino
www.DataSheet4U.com
ICS94209
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Jitter Cyc-Cyc
RDSP4B1
RDSN4B1
VOH4B
VOL4B
IOH4B
IOL4B
tr4B
tf4B
dt4B
tsk1
tjcyc-cyc1
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
12 55 Ω
12 55 Ω
2V
0.4 V
-19 mA
19 mA
0.5 1.5 2 ns
0.5 1.6 2 ns
45 52.3 55
%
55.5 175 ps
239 500 ps
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
VOH5
VOL5
IOH5
IOL5
tr5
tf5
dt5
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2.4
0.4
-22
16
1.8 4
1.9 4
45 54.5 55
1Guaranteed by design, not 100% tested in production.
UNITS
V
V
mA
mA
ns
ns
%
www.DataSheet4U.com
Third party brands and names are the property of their respective owners.
11

11 Page







PáginasTotal 19 Páginas
PDF Descargar[ Datasheet ICS94209.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS94201Programmable System Frequency GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS94203Programmable System Frequency GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS94206Programmable System Frequency GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS94209Programmable Frequency Generator & Integrated BuffersIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar