PDF ICS570A Data sheet ( Hoja de datos )

Número de pieza	ICS570A
Descripción	Multiplier and Zero Delay Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com ICS570A Multiplier and Zero Delay Buffer Description The ICS570A is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. ICS introduced the world standard for these devices in 1992 with the debut of the AV9170. The ICS570A, part of ICS’ ClockBlocks™ family, was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The chip has an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into the high impedance state. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing off-chip feedback paths, the ICS570A can eliminate the delay through other devices. The ICS570A was done to improve jitter from the original ICS570, and so it is recommended for all new designs. Features • Packaged in 8 pin SOIC. • Pin-for-pin replacement and upgrade to ICS570 • Functional equivalent to AV9170 (not a pin- for-pin replacement). • Low input to output skew of 500 ps max. • Low skew (250 ps) outputs. One is ÷ 2 of other. • Ability to choose between 14 different multipliers from 0.5X to 32X. • Input clock frequency up to 150 MHz at 3.3V. • Can recover poor input clock duty cycle. • Output clock duty cycle of 45/55. • Power Down and Tri-State Mode. • Full CMOS clock swings with 25mA drive capability at TTL levels. • Advanced, low power CMOS process. • Operating voltage of 3.0 to 5.5 V. • Industrial temperature version available Block Diagram ICLK S1, S0 FBIN 2 divide by N Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator ÷2 Output Buffer Output Buffer CLK CLK/2 External feedback can come from CLK or CLK/2 (see table on page 2). www.DataSheet4U.com MDS 570A C 1 Revision 102700 Printed 11/14/00 Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com 1 page www.DataSheet4U.com Recommended Circuit: S1 VDD GND INPUT FBIN S0 ICS570A Multiplier and Zero Delay Buffer CLK CLK/2 ICLK CLK CLK/2 x2 Mode (S1, S0 = 1, 1) CLK Feedback ICK CLK CLK/2 x2 Mode (S1, S0 = 1, 0) CLK/2 Feedback Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. But the CLK/2 could be a falling edge compared with ICLK. Therefore, wherever possible, we recommend the use of CLK/2 feedback. This will synchronize the rising edges of all 3 clocks. www.DataSheet4U.com MDS 570A C 5 Revision 102700 Printed 11/14/00 Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com 5 Page

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