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PDF DM9161 Data sheet ( Hoja de datos )
| Número de pieza | DM9161 | |
| Descripción | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1. General Description
The DM9161 is a physical layer, single-chip, and low
power transceiver for 100BASE-TX and 10BASE-T
operations. On the media side, it provides a direct
interface either to Unshielded Twisted Pair Category 5
Cable (UTP5) for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. Through
the Media Independent Interface (MII), the DM9161
connects to the Medium Access Control (MAC) layer,
ensuring a high inter operability from different vendors.
The DM9161 uses a low power and high performance
CMOS process. It contains the entire physical layer
functions of 100BASE-TX as defined by IEEE802.3u,
including the Physical Coding Sublayer (PCS),
Physical Medium Attachment (PMA), Twisted Pair
Physical Medium Dependent Sublayer (TP-PMD),
10BASE-TX Encoder/Decoder (ENC/DEC), and
Twisted Pair Media Access Unit (TPMAU). The
DM9161 provides a strong support for the auto-
negotiation function, utilizing automatic media speed
and protocol selection. Furthermore, due to the built-in
wave shaping filter, the DM9161 needs no external
filter to transport signals to the media in 100BASE-TX
or 10BASE-T Ethernet operation.
2. Block Diagram
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-TX
PCS
MII
Interface
10Base-T
TX/RX Module
Auto-Negotiation
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
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Final
Version: DM9161-DS-F02
May 10,2002
1
1 page  
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
4. Pin Configuration: DM9161 LQFP
RXDV/TESTMODE
RXER/RXD[4]/RPTR
DVDD
RESET#
DVDD
XT2
XT1
DGND
NC
AGND
BGRESG
BGRES
37
38
39
40
41
42
43
44
45
46
47
48
DM9161
24 MDC
23 DVDD
22 TXCLK/ISOLATE
21 TXEN
20 TXD[0]
19 TXD[1]
18 TXD[2]
17 TXD[3]
16 TXER/TXD[4]
15 DGND
14 CABLESTS/LINKSTS
13 LINK/ACTLED#/OP2
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Final
Version: DM9161-DS-F02
May 10,2002
5
5 Page 
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
6. LED Configuration
LEDs flash once per 500ms after power-on reset or
software reset by writing PHY register. All LED pins
are dual function pins, which can be configured as
either active high or low by pulling them low or high
accordingly. If the pin is pulled high, the LED is active
low after reset. Likewise, if the pin is pulled low, the
LED is active high.
DM9161
Pull High for
Reset
DVDD
300 Ohm
10K Ohm
Pull Low for
Reset
300 Ohm
10K Ohm
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Final
Version: DM9161-DS-F02
May 10,2002
11
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet DM9161.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DM9161 | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER | DAVICOM |
| DM9161A | 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER | DAVICOM |
| DM9161B | 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver | DAVICOM |
| DM9161BI | Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver | DAVICOM |
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