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PDF DM9101 Data sheet ( Hoja de datos )
| Número de pieza | DM9101 | |
| Descripción | 10/100Mbps Ethernet Physical Layer Single Chip Transceiver | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DM9101 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
General Description
The DM9101 is a physical-layer, single-chip, low-power
transceiver for 100Base-TX, and 10Base-T operations. On
the media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5) for
100Base-TX Fast Ethernet, or UTP5/UTP3 Cable for
10Base-T Ethernet. Through the IEEE 802.3u Media
Independent Interface (MII), the DM9101 connects to the
Medium Access Control (MAC) layer, ensuring a high inter-
operability among products from different vendors.
The DM9101 uses a low-power and high-performance
CMOS process. It contains the entire physical layer
functions of 100Base-TX as defined by IEEE 802.3u,
including the Physical Coding
Sublayer (PCS), Physical Medium Attachment (PMA),
100Base-TX Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD), and a 10Base-T Encoder/Decoder
(ENC/DEC). The DM9101 provides strong support for the
Auto-negotiation function utilizing automatic media speed
and protocol selection. The DM9101 incorporates an
internal wave-shaping filter to control rise/fall time,
eliminating the need for external filtering on the 10/100Mbps
signals.
Patent-Pending Circuitry Includes:
Smart adaptive receiver equalizer
Digital algorithm for high frequency clock/data recovery
circuit
High speed wave-shaping circuit
Block Diagram
25M OSCI
TX CGM
LED1-4#
LED
Driver
MII
Signals
MII
Interface/
Control
4B/5B
Encoder
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
100TXD+/-
4B/5B
Decoder
Code-
group
Alignment
25M CLK
Rise/Fall
Time
CTL
125M CLK
Descrambler
Serial to
Parallel
Digital
Logic
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
RXI+/-
10BASE-T
Module
RX
TX
RXI+/-
10TXD+/-
Register
Collision
Detection
Carrier
Sense
Auto-
Negotiation
Finwalww.DataSheet4U.com
Version: DM9101-DS-F03
July 22, 1999
1
1 page  
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Pin Description
Pin No.
LQFP QFP
MII Interface
54 56
55-58 57 - 60
61 63
62 64
63 65
64 66
67-70 69 - 72
73 75
Pin Name
TX_ER/
TXD4
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
MDC
MDIO
RXD3
RXD2
RXD1
RXD0
RX_CLK
DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
I/O Description
I Transmit Error:
In 100Mbps mode, if this signal is asserted high and TX_EN is
active, the HALT symbol is substituted for the actual data nibble.
In 10Mbps mode, this input is ignored.
In bypass modes (BP4B5B or BPALIGN), TX_ER becomes the
TXD4 pin, the fifth TXD data bit.
I Transmit Data:
Transmit data input pins for nibble data from the MII in 100Mbps
or 10Mbps nibble mode (25 MHz for 100Mbps mode, 2.5MHz for
10Mbps nibble mode).
In 10Mbps serial mode, the TXD0 pin is used as the serial data
input pin. TXD[3:1] are ignored.
I Transmit Enable:
Active high input indicates the presence of valid nibble data on
TXD[3:0] for both 100Mbps or 10Mbps nibble mode.
In 10Mbps serial mode, active high indicates the presence of
valid 10Mbps data on TXD0.
O,Z Transmit Clock:
Transmit clock output from the DM9101:
- 25MHz nibble transmit clock derived from transmit Phase
Locked Loop(TX PLL) in 100Base-TX mode
- 2.5MHz transmit clock in 10Base-T nibble mode
- 10MHz transmit clock in 10Base-T serial mode
I Management Data Clock:
Synchronous clock to the MDIO management data input/output
serial interface which is asynchronous to transmit and receive
clocks. The maximum clock rate is 2.5MHz.
I/O Management Data I/O:
Bi-directional management instruction/data signal that may be
driven by the station management entity or the PHY. This pin
requires a 1.5KΩ pull-up resistor.
O,Z Receive Data:
Nibble wide receive data (synchronous to RX_CLK - 25MHz for
100Base-TX mode, 2.5MHz for 10Base-T nibble mode). Data is
driven on the falling edge of RX_CLK.
In 10Mbps serial mode, the RXD0 pin is used as the data output
pin. RXD[3:1] are ignored.
O,Z Receive Clock:
Provides the recovered receive clock for different modes of
operation:
- 25MHz nibble clock in 100Mbps mode
- 2.5MHz nibble clock in 10Mbps nibble mode
- 10MHz receive clock in 10Mbps serial mode
Finwalww.DataSheet4U.com
Version: DM9101-DS-F03
July 22, 1999
5
5 Page 
www.DataSheet4U.com
Pin Description (continued)
DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Power and Ground Pins :
The power (VCC) and ground (GND) pins of the DM9101 are grouped in pairs of two categories - Digital
Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair.
Pin No.
Pin Name
I/O
Description
LQFP QFP
Group A - Digital Supply Pairs
35, 36,
37, 43,
50, 59,
65, 71,
84
37, 38,
39, 45,
52, 61,
67, 73,
86
DGND
P Digital Logic Ground.
Group A - Digital Supply Pairs (continued)
38, 47,
60, 72,
66, 85
40, 49,
62, 74,
68, 87
DVCC
P Digital Logic power supply
Group B - Analog Circuit Supply Pairs
4, 9,
10, 15,
16, 21,
22, 29,
32, 97,
98
6, 11, 12,
18, 17,
23, 24,
31, 34,
99, 100
AGND
P Analog circuit ground
5, 6,
13, 14,
19, 20,
25, 26,
31, 99
1, 7, 8,
15, 16,
21, 22,
27, 28, 33
AVCC
P Analog circuit power supply
Finwalww.DataSheet4U.com
Version: DM9101-DS-F03
July 22, 1999
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9101.PDF ] | |
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