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PDF HD64F3067 Data sheet ( Hoja de datos )
| Número de pieza | HD64F3067 | |
| Descripción | Hardware Manual | |
| Fabricantes | Renesas | |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
The H8/3067 Series is a series of high-performance single-chip microcontrollers that integrate
system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and
other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart
card interface. Functions have also been added to reduce power consumption in battery-powered
applications: individual modules can be placed in standby, and the frequency of the system clock
supplied to the chip can be divided down under software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3067 Series offers easy implementation of compact, high-performance
systems.
In addition to its mask ROM versions, the H8/3067 Series has an F-ZTAT™* version with on-
chip flash memory that can be programmed on-board. This version enables users to respond
quickly and flexibly to changing application specifications.
This manual describes the H8/3067 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Hitachi, Ltd.
5 Page 
6.11 Register and Pin Input Timing .......................................................................................... 196
6.11.1 Register Write Timing.......................................................................................... 196
6.11.2 BREQ Pin Input Timing....................................................................................... 197
Section 7 DMA Controller.............................................................................................. 199
7.1 Overview............................................................................................................................ 199
7.1.1 Features ................................................................................................................ 199
7.1.2 Block Diagram...................................................................................................... 200
7.1.3 Functional Overview ............................................................................................ 201
7.1.4 Input/Output Pins.................................................................................................. 202
7.1.5 Register Configuration ......................................................................................... 202
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 204
7.2.1 Memory Address Registers (MAR)...................................................................... 204
7.2.2 I/O Address Registers (IOAR) ............................................................................. 205
7.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 205
7.2.4 Data Transfer Control Registers (DTCR) ............................................................ 207
7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 210
7.3.1 Memory Address Registers (MAR)...................................................................... 210
7.3.2 I/O Address Registers (IOAR) ............................................................................. 210
7.3.3 Execute Transfer Count Registers (ETCR) .......................................................... 211
7.3.4 Data Transfer Control Registers (DTCR) ............................................................ 213
7.4 Operation ........................................................................................................................... 219
7.4.1 Overview .............................................................................................................. 219
7.4.2 I/O Mode .............................................................................................................. 221
7.4.3 Idle Mode.............................................................................................................. 223
7.4.4 Repeat Mode ........................................................................................................ 226
7.4.5 Normal Mode........................................................................................................ 229
7.4.6 Block Transfer Mode............................................................................................ 232
7.4.7 DMAC Activation ................................................................................................ 237
7.4.8 DMAC Bus Cycle ................................................................................................ 239
7.4.9 Multiple-Channel Operation ................................................................................ 245
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 246
7.4.11 NMI Interrupts and DMAC.................................................................................. 247
7.4.12 Aborting a DMAC Transfer ................................................................................. 248
7.4.13 Exiting Full Address Mode .................................................................................. 249
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 250
7.5 Interrupts............................................................................................................................ 251
7.6 Usage Notes ....................................................................................................................... 252
7.6.1 Note on Word Data Transfer ................................................................................ 252
7.6.2 DMAC Self-Access.............................................................................................. 252
7.6.3 Longword Access to Memory Address Registers ................................................ 252
7.6.4 Note on Full Address Mode Setup ....................................................................... 252
7.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 253
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