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PDF HD64F3064 Data sheet ( Hoja de datos )
| Número de pieza | HD64F3064 | |
| Descripción | Hardware Manual | |
| Fabricantes | Renesas | |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
The H8/3064F is a series of high-performance single-chip microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM (flash memory), RAM, 16-bit timers, 8-bit timers,
a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.
The two SCI channels support the ISO/IEC7816-3 smart card interface as an extended function.
Functions have also been added to reduce power consumption in battery-powered applications:
individual modules can be placed in standby mode, and the frequency of the system clock supplied
to the chip can be divided under program control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently for each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of initial data bus
width and address space size.
With these features, the H8/3064F enables easy implementation of compact, high-performance
systems.
The H8/3064F has an F-ZTAT™* version with on-chip flash memory that can be programmed
on-board. This version offers flexibility in the development of new products to meet fast-changing
market needs.
This manual describes the H8/3064F hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
5 Page 
Section 9 8-Bit Timers ..................................................................................................... 261
9.1 Overview............................................................................................................................ 261
9.1.1 Features ................................................................................................................ 261
9.1.2 Block Diagram...................................................................................................... 262
9.1.3 Pin Configuration ................................................................................................. 263
9.1.4 Register Configuration ......................................................................................... 264
9.2 Register Descriptions......................................................................................................... 265
9.2.1 Timer Counters (TCNT)....................................................................................... 265
9.2.2 Time Constant Registers A (TCORA) ................................................................. 266
9.2.3 Time Constant Registers B (TCORB).................................................................. 267
9.2.4 Timer Control Register (TCR) ............................................................................. 268
9.2.5 Timer Control/Status Registers (TCSR) .............................................................. 270
9.3 CPU Interface .................................................................................................................... 273
9.3.1 8-Bit Registers...................................................................................................... 273
9.4 Operation ........................................................................................................................... 275
9.4.1 TCNT Count Timing............................................................................................ 275
9.4.2 Compare Match Timing ....................................................................................... 276
9.4.3 Input Capture Signal Timing................................................................................ 277
9.4.4 Timing of Status Flag Setting............................................................................... 278
9.4.5 Operation with Cascaded Connection .................................................................. 279
9.4.6 Input Capture Setting............................................................................................ 282
9.5 Interrupt ............................................................................................................................. 283
9.5.1 Interrupt Sources .................................................................................................. 283
9.5.2 A/D Converter Activation .................................................................................... 284
9.6 8-Bit Timer Application Example ..................................................................................... 284
9.7 Usage Notes ....................................................................................................................... 285
9.7.1 Contention between TCNT Write and Clear........................................................ 285
9.7.2 Contention between 8TCNT Write and Increment .............................................. 286
9.7.3 Contention between TCOR Write and Compare Match ...................................... 287
9.7.4 Contention between TCOR Read and Input Capture ........................................... 288
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 289
9.7.6 Contention between TCOR Write and Input Capture .......................................... 290
9.7.7 Contention between TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection) ........................................................................................ 291
9.7.8 Contention between Compare Matches A and B ................................................. 292
9.7.9 TCNT Operation and Internal Clock Source Switchover .................................... 292
Section 10 Programmable Timing Pattern Controller (TPC).................................. 295
10.1 Overview............................................................................................................................ 295
10.1.1 Features ................................................................................................................ 295
10.1.2 Block Diagram...................................................................................................... 296
10.1.3 TPC Pins............................................................................................................... 297
10.1.4 Registers ............................................................................................................... 298
vi
11 Page | ||
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| PDF Descargar | [ Datasheet HD64F3064.PDF ] | |
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