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PDF AC39LV010 Data sheet ( Hoja de datos )
| Número de pieza | AC39LV010 | |
| Descripción | 1M Flash Memory | |
| Fabricantes | AS | |
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AC39LV010
AC39LV010
1 Megabit (128K x 8) Flash Memory
Single Power Supply
End-of-Program or End-of-Erase Detection
− Full voltage range: 2.7 to 3.6 volts for both read − Data# Polling
and write operations
− Toggle Bit
− Regulated voltage range : 3.0 to 3.6 volts for both
read and write operations
Sector-Erase Capability
CMOS I/O Compatibility
Uniform 4Kbyte sectors
Read Access Time
JEDEC Standard
Access time: 45, 70 and 90 ns
Pin-out and software command sets compatible with
Power Consumption
single-power supply Flash memory
High Reliability
− Active current: 5 mA (Typical)
− Standby current: 1 µA (Typical)
Erase /Program Features
− Endurance cycles: 100K (Typical)
− Data retention: 10 years
Package Option
− Sector-Erase Time: 40 ms (Typical)
− Chip-Erase Time: 40 ms (Typical)
− Byte-Program Time: 11µs (Typical)
− Chip Rewrite Time: 1.5 seconds (Typical)
− 32-lead PLCC
− 32-pin TSOP
− 48-pin FBGA
Automatic Write Timing
Internal VPP Generation
PRODUCT DESCRIPTION
The AC39LV010 is an 1M bits Flash memory organized as 128K x 8 bits . The AC39LV010 uses single
3.0 volt-only power supply for both Read and Write functions. Featuring high performance Flash memory
technology, the AC39LV010 provides a typical Byte-Program time of 11 µsec and a typical Sector -Erase time
of 40 ms. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase
operation. To protect against inadvertent write, the device has on-chip hardware and software data
protection schemes. The device offers typical 100,000 cycles endurance and a great er than 10 years data
retention. The AC39LV010 conforms to JEDEC standard pin outs for x8 memories. The AC39LV010 is
offered in package types of 32-lead PLCC, 32 -pin TSOP, 48-ball FBGA, and known good die (KGD). For
KGD, please contact Actrans System Inc. or its representatives for detailed information.
The AC39LV010 devices are developed for applications that require memories with convenient and
economical updating of program, data or configurations, e.g., Networking cards, Card Readers, Graphic
cards, Digital TV, MP3, Wireless Phones, etc.
Contact Information for Actrans System Inc.
2F, No. 9, Industry E. Rd. IV
Science Based Industrial Park
Hsinchu 300, Taiwan, R.O.C.
Tel. (+886-3) 577-8366
Fax. (+886-3) 577-8369
E-mail. service@actrans -inc.com
Website. www.actrans -inc.com
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This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (06/04/04)
Page 1
1 page  
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AC39LV010
Table 1. PIN DESCRIPTION
Name of the Pin
Function
A0–A16
17 addresses
DQ7–DQ0
Data inputs/outputs
CE# Chip enable
OE#
Output enable
WE#
Write enable
VDD 3.0 volt-only single power supply*
VSS Device ground
NC Pin not connected internally
* Note : see ordering information (page.2) for speed options
and voltage supply tolerances
DEVICE OPERATION
The AC39LV010 uses Commands to initiate the memory operation functions. The Commands are
written to the device by asserting WE# Low while keeping CE# Low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or
CE#, whichever occurs first.
Read
The Read operation of the AC39LV010 is controlled by CE# and OE#, both have to be Low for the
system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is
deselected and only standby power is consumed. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read
cycle timing diagram in Figure 1 for further details.
Byte Program
The AC39LV010 is programmed on a byte-by-byte basis. Before programming, the sector where the
byte locates must be erased completely. The Program operation is accomplished in three steps. The first
step is a three-byte load sequence for Software Data Protection. The second step is to load byte address
and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge
of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed
within 16 µs. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams and
Figure 12 for flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform additional tasks. Any commands issued during the
internal Program operation are ignored.
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This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/4/04)
Page 5
5 Page 
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AC39LV010
A16~A0
CE#
OE#
WE#
DQ7-0
TRC
TAA
TCE
TOE
V IH
HIGH-Z
TOLZ
T CLZ
TOH
Data Valid
TOHZ
TCHZ
Data Valid
HIGH-Z
Figure 1. Read Cycle Timing Diagram
A16~A0
WE#
OE#
5555
2AAA
TAH
TW P
TWPH
TA S
5555
ADDR
TDS
Internal Program Operation Starts
TBP
TDH
CE#
DQ7-0
TCH
AA
SW0
TCS
55
SW1
A0 DATA
SW2
Byte
(ADDR/DATA)
Figure 2. WE# Controlled Program Cycle Timing Diagram
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This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/4/04)
Page 11
11 Page | ||
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| PDF Descargar | [ Datasheet AC39LV010.PDF ] | |
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