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PDF 24W08 Data sheet ( Hoja de datos )
| Número de pieza | 24W08 | |
| Descripción | ST24W08 | |
| Fabricantes | ST Microelectronics | |
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Hay una vista previa y un enlace de descarga de 24W08 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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ST24C08, ST25C08
ST24W08, ST25W08
8 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x08 versions
– 2.5V to 5.5V for ST25x08 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W08 and ST25W08
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES)
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 8 Kbits I2C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control ver-
sion.
Table 1. Signal Names
PRE
E
SDA
SCL
MODE
WC
VCC
VSS
Write Protect Enable
Chip Enable Input
Serial Data Address Input/Output
Serial Clock
Multibyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
E
PRE
SCL
MODE/WC*
ST24x08
ST25x08
SDA
VSS
AI00860E
Note: WC signal is only available for ST24/25W08 products.
February 1999
1/16
1 page  
ST24/25C08, ST24/25W08
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance (SDA)
CIN Input Capacitance (other pins)
ZWCL
WC Input Impedance (ST24/25W08)
VIN ≤ 0.3 VCC
ZWCH
WC Input Impedance (ST24/25W08)
VIN ≥ 0.7 VCC
tLP
Low-pass filter input time constant
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.
Min Max Unit
8 pF
6 pF
5 20 kΩ
500 kΩ
100 ns
Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
ILO Output Leakage Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
SDA in Hi-Z
Supply Current (ST24 series)
ICC
Supply Current (ST25 series)
ICC1
Supply Current (Standby)
(ST24 series)
ICC2
Supply Current (Standby)
(ST25 series)
VIL Input Low Voltage (SCL, SDA)
VIH Input High Voltage (SCL, SDA)
VIL
Input Low Voltage
(E, PRE, MODE, WC)
VCC = 5V, fC = 100kHz
(Rise/Fall time < 10ns)
VCC = 2.5V, fC = 100kHz
VIN = VSS or VCC,
VCC = 5V
VIN = VSS or VCC,
VCC = 5V, fC = 100kHz
VIN = VSS or VCC,
VCC = 2.5V
VIN = VSS or VCC,
VCC = 2.5V, fC = 100kHz
–0.3
0.7 VCC
–0.3
VIH
Input High Voltage
(E, PRE, MODE, WC)
VCC – 0.5
VOL Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V
Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V
Max
±2
±2
2
1
100
300
5
50
0.3 VCC
VCC + 1
0.5
VCC + 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
5/16
5 Page 
ST24/25C08, ST24/25W08
Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W08)
WC
BYTE WRITE
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01161B
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
Random Address Read. A dummy write is per-
formed to load the address into the address counter
(see Figure 11). This is followed by another START
condition from the master and the byte address is
repeated with the RW bit set to ’1’. The memory
acknowledges this and outputs the byte ad-
dressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 24W08.PDF ] | |
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