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PDF MX98224EC Data sheet ( Hoja de datos )
| Número de pieza | MX98224EC | |
| Descripción | 24-port Dual-Speed Ethernet Switch Controller | |
| Fabricantes | MXIC | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
PRELIMINARY
MX98224EC
24-port Dual-Speed Ethernet Switch Controller
FEATURES
l Single chip 24-port 10/100M wire speed Ethernet
switching controller with all memory embedded
l Integration of 24-port dual speed, full/half duplex
capable Media Access Controllers (MACs) with RMII
interfaces
l Support IEEE 802.3x compliant flow control for FDX
and back-pressure flow control for HDX
l Auto-negotiation through MDC/MDIO
l Support source/destination MAC address lookup and
aging within built-in storage of 8K MAC address (4K
entries each entry table)
l Self address learning, forwarding, and filtering
schemes
l Store-and-Forward switching operation
l 12-group port base VLAN with port overlapping
l IEEE 802.1q CoS and two priority queues support
based on port, tagging, and TOS configurations
l Address table and PHY register access allowed
through CPU processor
l Dynamic buffer management
l No head-of-line blocking system support
l Power on self diagnostic
l Serial EEPROM (93C46) interface for auto-
configuration
l Broadcast storm prevention
l Serial CPU interface support for system configuration
required
l Three alter/self-diagnostic LED interface
l CMOS, 1.8/3.3V I/O tolerance
l 208 PQFP package
GENERAL DESCRIPTION
MX98224EC is a stand-alone 10/100M Ethernet switch
controller with SRAM embedded which saves 2-3 extra
64KX64 SRAM cost. Any standalone desktop or
enterprising Ethernet switches can be achieved by
simply combining MX98224EC and quad/octal physical
devices. All 24 ports are full duplex capable to provide
dedicated 20/200M bandwidth connections each port.
MX98224EC basically supports store-and-forward
switching scheme with two address entry tables, 4K size
each. The function modules integrated in controller
include 24-port half/full-duplex compatible media access
controller with RMII interface, address resolution logic
(ARL) for address learning, filtering, recognition, priority
queue manager, port base VLAN. It fully complies with
IEEE Std. 802.3/802.3u/802.1q specifications and
supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
The switch architecture adopting dynamic buffer
management shared by 24 ports can reach full-line
speed of high performance application. To save
system cost, single 50Mhz clock is for RMII and system
requirement. MX98224EC proceeds in advanced
foundry and smaller package which consumes lower
power dissipation.
The smart features with low power CPU or EEPROM
are for system configuration and ALR access required.
Also, it emphasizes at Class of Service (CoS) which
extracts various packet types in appropriate forwarding
scheme. Now, Voice over IP (VoIP) is applied the
feature for cutting voice packet latency and promise the
quality of service. In addition, port-base VLAN is
another valuable feature for the switches. MX98224EC
offers 12 groups with port overlapping allowed. The
feature can add on more security and data flow in the
same switch with different groups should get connection
through router. The powerful switching architecture
and robust design can easily reach high performance,
non-blocking data flow.
Head-of-line blocking prevents switch performance, and
operation defective from other port impacts. The switch
architecture provides a clean port independent
operation. It guarantees port transmission or receive
is not affected by other ports.
Moreover, user can discard broadcast packets regarding
the threshold of system overload. This prevents
potential broadcast storming from abnormal events.
After buffer fullness drops in the safe margin, the switch
controller jumps into flow control state to allow physical
ports work as normal condition.
MX98224EC provides self on test as soon as power on
or reset. It will detect all buffer memory and address
table and others. If defective, LED is automatically on.
Several LEDs are defined in switch controller like status
of broadcast storm, packet loss, and buffer full.
P/N:PM0782
www.DataSheet4U.com
1
REV. 0.2, Apr, 18, 2001
1 page  
PIN DESCRIPTION
10/100Mbps RMII INTERFACE
PIN#
PIN NAME
I/O
4 CRSDV_0
10 CRSDV_1
18 CRSDV_2
24 CRSDV_3
30 CRSDV_4
38 CRSDV_5
44 CRSDV_6
52 CRSDV_7
58 CRSDV_8
66 CRSDV_9
72 CRSDV_10
81 CRSDV_11
89 CRSDV_12
95 CRSDV_13
103 CRSDV_14
109 CRSDV_15
115 CRSDV_16
123 CRSDV_17
129 CRSDV_18
137 CRSDV_19
143 CRSDV_20
154 CRSDV_21
160 CRSDV_22
166 CRSDV_23
I
6, 5
12, 11
20, 19
26, 25
32, 31
40, 39
46, 45
54, 53
60, 59
68, 67
76, 73
83, 82
91, 90
99, 98
105, 104
111, 110
117, 116
125, 124
131, 130
139, 138
149, 144
156, 155
162, 161
168, 167
RXD_0[1:0]
RXD_1[1:0]
RXD_2[1:0]
RXD_3[1:0]
RXD_4[1:0]
RXD_5[1:0]
RXD_6[1:0]
RXD_7[1:0]
RXD_8[1:0]
RXD_9[1:0]
RXD_10[1:0]
RXD_11[1:0]
RXD_12[1:0]
RXD_13[1:0]
RXD_14[1:0]
RXD_15[1:0]
RXD_16[1:0]
RXD_17[1:0]
RXD_18[1:0]
RXD_19[1:0]
RXD_20[1:0]
RXD_21[1:0]
RXD_22[1:0]
RXD_23[1:0]
I
MX98224EC
DESCRIPTION
Carrier Sense/Receive Data Valid
Active high, indicate receive medium is non-idle. CRSDV is asserted
asynchronously with respect to CLK.
Receive Data
From Port 0 to Port 23, synchronous to CLK and RXD[1] is MSB.
While CRSDV is deasserted, RXD[1:0] is “00”.
P/N:PM0782
REV. 0.2, Apr, 18, 2001
5
5 Page 
Port Base VLAN Group 0 (0-11) (Reg00H), default = 0x0FFFH
BIT
0.11-0
0.15-12
DESCRIPTION
Port 0-11 VLAN Group 0
Default 1; all ports are into single group.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 0 member
N/A
Port Base VLAN Group 0 (12-23) (Reg01H), default = 0x0FFFH
BIT
1.11-0
1.15-12
DESCRIPTION
Port 12-23 VLAN Group 0
Default 1; all ports are into single group.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 0 member
N/A
Port Base VLAN Group 1 (0-11) (Reg02H), default = 0x0000H
BIT
2.11-0
2.15-12
DESCRIPTION
Port 0-11 VLAN Group 1
Default 0; group 1 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 1 member
N/A
Port Base VLAN Group 1 (12-23) (Reg03H), default = 0x0000H
BIT
3.11-0
3.15-12
DESCRIPTION
Port 12-23 VLAN Group 1
Default 0; group 1 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 1 member
N/A
MX98224EC
TYPE
R/W
DEFAULT
0xFFF
TYPE
R/W
DEFAULT
0xFFF
TYPE
R/W
DEFAULT
0x000
TYPE
R/W
DEFAULT
0x000
P/N:PM0782
REV. 0.2, Apr, 18, 2001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX98224EC.PDF ] | |
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