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PDF ICS651-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS651-03 | |
| Descripción | VOIP Clock Source | |
| Fabricantes | Integrated Circuit Systems | |
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( DataSheet : www.DataSheet4U.com )
ICS651-03
VOIP Clock Source
Description
The ICS651-03 is a low cost frequency generator
designed to support voice-over-internet protocol
(VOIP) applications. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device uses
a standard fundamental mode, inexpensive crystal
input to produce four output clocks supporting DSP,
video encoder, and memory functions. To form a
complete VOIP clocking solution use the ICS651-02
companion device.
The device also has a power down feature that
tri-states the clock outputs and turns off the PLL when
the PDTS pin is taken low.
Features
• Packaged in 16-pin TSSOP
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 27 MHz
• Fixed reference output frequency of 80 MHz
• Fixed output frequency of 48 MHz
• Fixed output frequency of 25 MHz
• Reference output frequency of 27 MHz
• Duty cycle of 40/60
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
VDD
6
PLL1
80M
X1
27 MHz
crystal
input
X2
Crystal
Oscillator/
Clock
Buffer
External capacitors
may be required.
PLL2
3
GND
48M
25M
REF
PDTS (all outputs and PLLs)
MDS 651-03 A
1
Revision 112603
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
www.DataSheet4U.com
1 page  
ICS651-03
VOIP Clock Source
Parameter
Nominal Output Impedance
Internal pull-up resistor
Internal pull-down resistor
Symbol
Conditions
ZOUT
RPU
RPD
PDTS pins
Min.
Typ.
20
700
200
Max.
Units
Ω
kΩ
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Input Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
fIN
tOR 20% to 80% (Note 1)
tOF 80% to 20% (Note 1)
at VDD/2 (Note 1)
40
Absolute Clock Period Jitter
(Note 1)
Frequency synthesis error
Output Enable Time
tOE PDTS high to output
locked to ±1%
Output Disable Time
tOD PDTS low to tri-state
Note 1: Measured with a 15 pF load.
Typ.
27
1.0
1.0
± 100
0
250
Max. Units
MHz
ns
ns
60 %
ps
ppm
µs
20 ns
MDS 651-03 A
5
Revision 112603
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICS651-03.PDF ] | |
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