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Integrated Circuit Systems - Networking Clock Source

Numéro de référence ICS650-27
Description Networking Clock Source
Fabricant Integrated Circuit Systems 
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ICS650-27 fiche technique
ICS650-27
Networking Clock Source
Description
The ICS650-27 is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 12.5 MHz or 25 MHz
clock or fundamental mode crystal input to produce
multiple output clocks for networking chips, PCI
devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V
designs.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other needed
clocks.
Features
Packaged in 20-pin (150 mil) SSOP (QSOP)
Available in Pb (lead) free package
12.5 MHz or 25 MHz fundamental crystal or clock
input
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive
capability at TTL levels
Advanced, low-power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature only
Block Diagram
ACS1:0
BCS1:0
CCS
2
2
25 or 12.5 MHz
cyrstal or clock
X1/ICLK
X2
VDD
2
Clock
Buffer/
Crystal
Oscillator
Clock
Synthesis
and Control
Circuitry
2
GND
CLKA1
/2 CLKA2
CLKB1
/2 CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
MDS 650-27 D
1
Revision 070505
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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