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PDF M37544G Data sheet ( Hoja de datos )
| Número de pieza | M37544G | |
| Descripción | Single-Chip 8-Bit CMOS Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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7544 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0012-0104Z
Rev.1.04
2004.06.08
DESCRIPTION
The 7544 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A/D converter, and is useful for control of home electric appli-
ances and office automation equipment.
FEATURES
• Basic machine-language instructions ...................................... 71
• The minimum instruction execution time ......................... 0.25 µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
• Memory size ROM ......................................................... 8 K bytes
RAM ........................................................ 256 bytes
• Programmable I/O ports ........................................................... 25
• Interrupts ................................................. 12 sources, 12 vectors
• Timers ............................................................................. 8-bit ✕ 2
...................................................................................... 16-bit ✕ 1
• Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
• A/D converter ................................................. 8-bit ✕ 6 channels
• Clock generating circuit ............................................. Built-in type
(low-power dissipation by an on-chip oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscilla-
tor permitting RC oscillation)
• Watchdog timer ............................................................ 16-bit ✕ 1
• Power source voltage
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
double-speed mode
At 8 MHz .................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
high-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
XIN oscillation frequency at RC oscillation
At 4 MHz .................................................................... 4.0 to 5.5 V
• Power dissipation ........................................... 22.5mW(standard)
• Operating temperature range ................................... –20 to 85 °C
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 P11/TXD
31 P10/RXD
30 P07(LED7)
29 P06(LED6)
28 P05(LED5)
27 P04(LED4)
26 P03(LED3)/TXOUT
25 P02(LED2)
24 P01(LED1)
23 P00(LED0)/CNTR1
22 P37(LED13)/INT0
21 P34(LED12)/INT1
20 P33(LED11)
19 P32(LED10)
18 P31(LED9)
17 P30(LED8)
Fig. 1 Pin configuration (32P4B type)
Package type : 32P4B
Rev.1.04 2004.06.08 page 1 of 66
REJ03B0012-0104Z
1 page  
7544 Group
Fig. 6 Functional block diagram (32P6U package)
Rev.1.04 2004.06.08 page 5 of 66
REJ03B0012-0104Z
5 Page 
7544 Group
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data trans-
fers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory lo-
cation 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal ad-
dressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.1.04 2004.06.08 page 11 of 66
REJ03B0012-0104Z
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M37544G.PDF ] | |
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