DataSheetWiki


54LS373 fiches techniques PDF

ETC - SN54LS373 / DM54LS373

Numéro de référence 54LS373
Description SN54LS373 / DM54LS373
Fabricant ETC 
Logo ETC 





1 Page

No Preview Available !





54LS373 fiche technique
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup times is latched. Data appears on the bus
www.DataSheet4wUh.ceonmthe Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-
ented applications. A buffered Clock (CP) and Output Enable (OE) is common
to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low
Power Schottky technology and is compatible with all Motorola TTL families.
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
D0 – D7
LE
CP
OE
O0 – O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH going edge) Input
Output Enable (Active LOW) Input
Outputs (Note b)
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.
SN54/74LS373
SN54/74LS374
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN54 / 74LS373
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54 / 74LS374
V CC O 7
20 19
D7 D6 O6 O5 D5 D4 O4
18 17 16 15 14 13
12
LE
11
V CC O 7 D 7 D 6 O 6 O 5 D 5 D 4 O 4 CP
20 19 18 17 16 15 14 13
12 11
12 3 4 56
7 8 9 10
OE O 0 D 0 D 1 O 1 O 2 D 2 D 3 O 3 GND
NOTE:
12 3 4 56
7 8 9 10
The Flatpak version
has the same pinouts
OE O 0 D 0 D 1 O 1 O 2 D 2 D 3 O 3 GND
(Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-521

PagesPages 7
Télécharger [ 54LS373 ]


Fiche technique recommandé

No Description détaillée Fabricant
54LS373 SN54LS373 / DM54LS373 ETC
ETC
54LS374 DM54LS374 National Semiconductor
National Semiconductor
54LS375 54LS375 ETC
ETC
54LS375 4-Bit Latch National Semiconductor
National Semiconductor

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche