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PDF TC58V64DC Data sheet ( Hoja de datos )
| Número de pieza | TC58V64DC | |
| Descripción | 16M-Bit CMOS NAND EPROM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC58V64DC
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64-MBIT (8M × 8 BITS) CMOS NAND E2PROM (8M BYTE SmartMediaTM)
DESCRIPTION
The TC58V64 is a single 3.3-V 64-Mbit (69,206,016) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes × 16 pages × 1024 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (8 Kbytes + 512 bytes: 528
bytes × 16 pages).
The TC58V64 is a serial-type memory device which utilizes the I/O pins for both address and data input/output
as well as for command inputs. The Erase and Program operations are automatically executed making the device
most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras
and other systems which require high-density non-volatile memory data storage.
The data stored in the TC58V64DC needs to comply with the data format standardized by the SSFDC Forum in
order to maintain compatibility with other SmartMediaTM systems.
FEATURES
• Organization
Memory cell array 528 × 16K × 8
Register
528 × 8
Page size
528 bytes
Block size
(8K + 512) bytes
• Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read
• Mode control
Serial input/output, Command control
• Complies with the SmartMediaTM Electrical
Specification and Data Format Specification
issued by the SSFDC Forum
• Power supply
VCC = 3.3 V ± 0.3 V
• Access time
Cell array-register
7 µs max
Serial Read cycle
50 ns min
• Operating current
Read (50-ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
100 µA max
• Package
TC58V64DC: FDC-22A (Weight: 1.8 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
VSS CLE ALE WE WP I/O1 I/O2 I/O3 I/O4 VSS VSS
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
I/O1~I/O8
CE
WE
RE
CLE
ALE
WP
RY/BY
GND
LVD
VCC
VSS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground Input
Low Voltage Detect
Power supply
Ground
VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC
TM
is a trademark of Toshiba Corporation.
000707EBA2
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2000-08-27 1/33
1 page  
Notes:
(1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (7) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns.
If the RE to CE delay is less than 30 ns, RY/BY signal stays Ready.
TC58V64DC
tCEH ≥ 100 ns
* *: VIH or VIL
CE
RE
525 526 527 A
RY/BY
Busy
A : 0~30 ns → Busy signal is not output.
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V)
SYMBOL
PARAMETER
MIN
tPROG
N
Programming Time
Number of Programming Cycles on Same
Page
tBERASE
P/E
Block Erasing Time
Number of Program/Erase Cycles
(1) Refer to Application Note 12 toward the end of this document.
(2) Refer to Application Note 15 toward the end of this document.
TYP.
200
2
MAX
1000
10
20
1 x 106
UNIT
µs
ms
NOTES
(1)
(2)
2000-08-27 5/33
5 Page 
Sequential Read (1) Timing Diagram
CLE
TC58V64DC
CE
WE
ALE
RE
I/O1
~I/O8
00H
RY/BY
A0~A7 A9~A16 A17~A22
Column Page
address address
NM
tR
N N + 1 N + 2 527
012
tR
Page M
access
Page M + 1
access
: VIH or VIL
Sequential Read (2) Timing Diagram
CLE
527
CE
WE
ALE
RE
I/O1
~I/O8
01H
RY/BY
A0~A7 A9~A16 A17~A22
527 0 1 2
Column Page
address address
NM
tR 256 + 256 + 256 +
N N+1 N+2
tR
527
Page M
access
Page M + 1
access
: VIH or VIL
2000-08-27 11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC58V64DC.PDF ] | |
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