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PDF LXT384 Data sheet ( Hoja de datos )
| Número de pieza | LXT384 | |
| Descripción | Octal T1/E1/J1 Short Haul PCM Transceiver | |
| Fabricantes | Intel | |
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Intel® LXT384 Octal T1/E1/J1 Short-Haul
PCM Transceiver with Jitter Attenuation
(JA)
Product Features
Datasheet
■ Octal T1/E1/J1 Pulse-Code Modulation ■ Transmitters
(PCM) Transceiver with Jitter Attenuation
for use in both 1.544 Mbps (T1) and 2.048
Mbps (E1) applications
■ 16 fully-independent receiver/transmitters
■ Support for E1 standards:
— Exceeds ETSI ETS 300 166
— Meets ETS 300 233
■ Low-power single-rail 3.3-V CMOS power
supply, with 5-V tolerant I/Os
■ Jitter attenuation
— Crystal-less
— Power-down mode with fast output
tristate capability
— Transmit waveform shaping meets ITU
G.703 and T1.102 specifications
— Exceeds ETSI ETS 300 166 transmit
return-loss specifications
— Low-impedance transmit drivers,
independent of transmit pattern and
supply-voltage variations
— Low-current transmit output option that
can reduce power dissipation by up to
— Digital clock recovery PLL
15%. By changing the LXT384
— Referenced to a low frequency 1.544
MHz or 2.048-MHz clock. Normal
operation requires only MCLK. Does
not require a reference clock frequency
higher than the line frequency.
— Can be switched between receive and
transmit path
— Meets ETSI CTR12/13, ITU G.736,
G.742, G.823, and AT&T Pub 62411
Transceiver output transformer ratio
from 1:2 to 1:1.7, the savings occur
whether TVCC is at 5 V or 3.3 V.
130 mW per channel (typical). See
Table 63 “Intel® LXT384 Transceiver
Power Consumption” on page 104 and
Table 64 “Load3 Power Consumption”
on page 105.
■ HDB3, B8ZS, or AMI line encoder/decoder
■ LOS per ITU G.775, T1.231, and ETS 300
— Optimized for Synchronous Optical
233
NETwork (SONET) and Synchronous ■ Diagnostics:
Digital Hierarchy (SDH) applications,
meets ITU G.783 mapping jitter standard
— Can be configured for G.722-compliant,
non-intrusive performance (protected)
— Constant throughput delay
monitoring points
■ Differential receiver architecture
— High margin for noise interference
— Operates at >12 dB of cable attenuation
■ Intel® Hitless Protection Switching
— Eliminates mechanical relays for
redundancy 1+1 protection applications
— Increases quality of service
— Industry-standard P1149.1 JTAG
Boundary Scan test port
■ Intel®/ Motorola* 8-bit parallel processor
interface or 4 wire serial control interface
■ Hardware and Software control modes
■ Operating temperature -40 °C to 85 °C
■ 160-ball PBGA or 144-pin LQFP packages
Applications
■ SONET/SDH tributary interfaces
■ Microwave transmission systems
■ Digital cross connects
■ M13, E1-E3 MUX www.DataSheet4U.com
■ Public/private switching trunk line interfaces
www.DataSheet4U.com
Document Number: 248994
Revision Number: 004
Revision Date: September 22, 2005
1 page  
Contents
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Line-Interface-Unit Circuit Specifications.................................................... 121
Mask Specifications .............................................................................................. 122
Jitter Performance ................................................................................................. 124
Recommendations and Specifications .........................................................129
Mechanical Specifications.................................................................................. 131
Abbreviations and Acronyms ........................................................................... 133
Figures
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Intel® LXT384 Transceiver High-Level Block Diagram........................................12
Intel® LXT384 Transceiver Detailed Block Diagram............................................ 13
Intel® LXT384 Transceiver LQFP Markings and 144-Pin Assignments ..............15
Intel® LXT384 Transceiver Plastic Ball Grid Array (PBGA) Pin Assignments ..... 16
50% AMI Encoding.............................................................................................. 51
Intel® LXT384 Transceiver External Transmit/Receive Line Circuitry ................. 56
Jitter Attenuator ................................................................................................... 58
Intel® LXT384 Transceiver Analog Loopback ..................................................... 60
Intel® LXT384 Transceiver Digital Loopback....................................................... 61
Intel® LXT384 Transceiver Remote Loopback ....................................................62
TAOS Data Path for Intel® LXT384 Transceiver ................................................. 63
TAOS with Analog Loopback for Intel® LXT384 Transceiver .............................. 64
TAOS with Digital Loopback for Intel® LXT384 Transceiver ............................... 64
Host Processor Mode - Serial Interface Read Timing ......................................... 71
JTAG Architecture ............................................................................................... 84
JTAG State Diagram ........................................................................................... 86
Analog Test Port Application ............................................................................... 91
JTAG Timing ....................................................................................................... 93
Intel® LXT384 Transceiver - Transmit Timing ................................................... 104
Intel® LXT384 Transceiver - Receive Timing .................................................... 106
Intel® Processor Non-Multiplexed Interface - Read Timing ...............................108
Intel® Processor Multiplexed Interface - Read Timing....................................... 109
Intel® Processor Non-Multiplexed Interface - Write Timing ...............................111
Intel® Processor Multiplexed Interface - Write Timing ....................................... 112
Motorola Processor Non-Multiplexed Interface - Read Timing.......................... 114
Motorola Processor Multiplexed Interface - Read Timing ................................. 115
Motorola Processor Non-Multiplexed Interface - Write Timing.......................... 117
Motorola Processor Multiplexed Interface - Write Timing.................................. 118
Serial Input Timing ............................................................................................ 119
Serial Output Timing..........................................................................................120
E1, ITU G.703 Mask Template .......................................................................... 122
T1, T1.102 Mask Templates for LXT384........................................................... 123
Intel® LXT384 Transceiver Jitter Tolerance Performance................................. 126
Intel® LXT384 Transceiver Jitter Transfer Performance ................................... 127
Intel® LXT384 Transceiver Output Jitter for ETSI CTR12/13 Applications........ 128
Dimensions for 144-Pin Low Octal Flat Package (LQFP) ................................. 131
Dimensions for 160-Ball Plastic Ball Grid Array (PBGA)................................... 132
Datasheet
Document Number: 248994
Revision Number: 004
Revision Date: September 22, 2005
5
5 Page 
2.0
Intel® LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Product Summary
The Intel® LXT384 Octal T1/E1/J1 Short-Haul Pulse-Code Modulation Transceiver with Jitter
Attenuation (called hereafter the LXT384 transceiver) is designed for use in 1.544 MBps (T1) or
2.048-Mbps (E1) applications. It incorporates eight independent receivers and eight independent
transmitters in either a single 144-pin LQFP or a 160-ball PBGA package.
Transmitters. The LXT384 transceiver transmits shaped waveforms that meet ITU G.703
specifications. The transmit drivers provide low impedance, independent of supply-voltage
variation and transmit patterns. The output of the transmitters is stable over a variety of loads. The
transmit return loss for the LXT384 transceiver exceeds typical specifications such as ETSI ETS
300 166. All transmitters have a power-down mode with the capability for a fast transition to an
output high-impedance tristate.
Power Savings. The Intel® transmit output design allows you to use the transmitter output of the
LXT384 Transceiver in a broad range of applications, while maintaining circuit stability. As a
result, the LXT384 Transceiver can offer a low-current transmit output option that can reduce
power dissipation by up to 15%. By changing the LXT384 Transceiver output transformer ratio
from 1:2 to 1:1.7, the savings occur whether TVCC is at 5V or 3.3V.
Receivers. The LXT384 Transceiver has a differential receiver architecture that provides a high
noise-interference margin so that the receivers can operate well beyond 12 dB of cable attenuation.
Jitter Attenuation. The LXT384 Transceiver incorporates a crystal-less jitter attenuator that can
be switched to work inside either the receive or the transmit path, or it can be disabled entirely. The
jitter-attenuation performance, optimized for synchronous digital hierarchy (SDH) applications,
meets typical international specifications such as ETSI CTR12/13.
Performance Monitoring. You can configure the LXT384 Transceiver for non-intrusive
performance monitoring (also known as ‘protected monitoring’) that is compliant with ITU G.772.
Intel® Hitless Protection Switching. The LXT384 Transceiver can operate in an Intel® Hitless
Protection Switching mode, which uses one transceiver to back up another, in case the primary
transceiver fails. This method is often referred to as 1+1 redundancy protection. Typical
redundancy methods used external relays. Intel® Hitless Protection Switching is a solid-state
solution, which reduces bit errors that can occur when using external relays for redundancy
protection. This mode uses two LXT384 Transceivers in parallel, with one LXT384 Transceiver
powered on, while the other LXT384 Transceiver is in standby mode. As a result, one LXT384
Transceiver backs up another LXT384 Transceiver. See the 1+1 Protection without Relays Using
Intel® LXT380/1/4/6/8 Hitless Protection Switching - Application Note.
Document Number: 248994
Revision Number: 004
Revision Date: September 22, 2005
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT384.PDF ] | |
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