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PDF IP3023 Data sheet ( Hoja de datos )
| Número de pieza | IP3023 | |
| Descripción | Wireless Network Processor | |
| Fabricantes | Ubicom | |
| Logotipo |  |
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PRELIMINARY
May 21, 2003
IP3023™ Wireless Network Processor
250 MIPS 8-Way Multithreaded Processor Optimized for Network Connectivity
1.0 Product Highlights
The IP3023™ wireless network processor is a revolutionary new
platform from Ubicom designed to provide highly integrated
solutions for applications at the "edge" of internet connectivity,
including 802.11a/b/g access points, routers, hot spots, bridges,
gateways, and a wide variety of embedded networked client
solutions. The IP3023 is optimized for efficient network
processing in embedded solutions. Its development has lead to
the definition of a new microprocessor architecture:
Multithreaded Architecture for Software I/O (MASI). Many MASI
concepts were pioneered in the Ubicom IP2000™ family of
processors, but the IP3023 dramatically extends those
techniques by introducing hardware support for multiple threads
operating with no context switching overhead, as well as t hree-
operand and memory-to-memory operations.
The IP3023 is a 250 MIPS 32-bit CPU supporting eight-way
multithreaded operation. It provides for up to eight real-time
tasks to execute in a completely deterministic fashion. In
essence, the IP3023 supports running a different thread on
every clock, but without the overhead for context switching
typical with traditional microprocessor architectures. To the
system designer, the IP3023 appears as if there were 8
processors on the chip.
The multithreaded and deterministic nature of the IP3023
processor provides for integration of numerous functions on-chip
– some with on-chip hardware assist and some entirely in
software – as threads, including the ability to support interfaces
such as 10/100 MII and 10base-T Ethernet MAC/PHY, USB,
GPSI, Utopia, PCMCIA, IDE, PCM Highway, and
Key Features:
• 250 MIPS, 32-bit MASI CPU
• IP3023 is optimized for wireless networking
• 8-way simultaneous multithreading
• Deterministic execution on all threads
• Zero overhead full context switching
• Programmable MIPS per thread
• Optimized ISA for packet processing
• Memory to memory architecture, powerful addressing modes
• Small fast instruction set, strong bit manipulation
• Reduced code size vs RISC CPUs
• On-chip Program and Data memory
• Eliminates cache miss penalties
• 256KB (64k x 32) of Program SRAM
• 64kB (16k x 32) of Data SRAM
• Highly configurable I/O support
• Many Combinations of Software I/O:
• Utopia, PCMCIA, IDE/ATAPI
• PCM Highway, UART, SPI, I2C
• 32-bit 802.11a/g radios interface
• Two SerDes for fast serial I/O:
• 10Base-T (MAC/PHY), USB, GPSI
• SPI, UART, 2-wire serial, BlueRF
• Up to 4 MII ports for 10/100 PHY
• Additional key hardware
• True random number generator for software-implemented
encryption/security (32-bit seed)
• Fixed-point MAC (16x16+48-bit, 250 MMACs) for voice/audio
codecs, other signal processing tasks
• Independent I/O and core CPU clocking
• Separate Phase-Locked Loops (PLLs)
• Programmable multipliers & dividers
• Single low cost crystal (10MHz)
IP3023
SYSTEM
AND
I/O
CLOCKS
CLK CNTRL 8-WAY MULTI- 64K x 32
16K x 32
(PLL Mult THREADED INSTRUCTION DATA
I/O and Sys) 32-BIT CPU
RAM
RAM
SYSTEM,
REAL-TIME,
WATCHDOG
TIMERS
MII x 4
(host and phy)
SerDes x 2
(10BT, USB,
SPI, UART,
etc.)
SDRAM
CONTROLLER
GPIO (802.11x Cardbus,
Utopia, PCM, I2C,
PCMCIA, ISA, etc.
possible)
FLASH
CONTROLLER
RANDOM
NUMBER
GENERATOR
32
PORT A
8
PORT B
i/O PORT SELECTOR
16 18 8
8
PORT C
PORT D
PORT E
PORT F
Figure 1-1 IP3023 Block Diagram
32
PORT G
16
PORT H IP3K-DDS
www.ubicom.com
© 2003 Ubicom, Inc. All rights reserved.
1
1 page  
IP3023 Technical Brief
1.3.3 CPU Data Memory
The data memory for the main processor is 64 KB (16K x
32) SRAM. It is able to perform one read and one write per
clock, in support of the three-operand and memory-to-
memory instruction set architecture.
1.3.4 I/O Ports
1.3.5 Clocks, Frequency, and Timers
A single clock input (crystal, 10–20 MHz) is used to source
multiple subsystems and peripherals in the IP3023. This
clock source is fed into independent PLLs for generating
a system clock and an I/O clock. Alternatively, the PLLs
can be bypassed, and the 10–20 MHz clock input can be
used directly. The PLLs are capable of generating up to a
250 MHz clock from the 10–20 MHz input signal.
This initial 10–20 MHz input is also fed into a real-time
clock (RTC) timer, which can be used to maintain an
accurate time base in a system.
1.3.6 Low Power Operation
Being fabricated in advanced process geometries and
operating off a 1.2V supply, the IP3023 is inherently
efficient in terms of low power operation. However, the
IP3023 can also be configured for additional levels of
power savings, based on varying the frequency of
operation and clock source. These lower power modes
can be used in combination with one another, and include:
• Reduce the clock frequency out of the system clock
PLL. The clock circuit of the IP3023 includes a run-
time controllable post-divider on the PLL output, al-
lowing the developer to drop the operating frequency
in steps down to 1/16 of the maximum operating fre-
quency (i.e. 250 MHz full active frequency can be re-
duced down to as little as 15.625 MHz).
• Reduce the clock frequency out of the I/O clock PLL.
As with the system clock PLL, the I/O clock PLL in-
cludes a run-time controllable post-divider at the out-
put, allowing for I/O clock frequency reduction on the
fly in steps down to 1/16 of the maximum operating
frequency.
• Turn off system clock PLL. System clocking runs di-
rectly from the 10–20 MHz clock input.
• Turn off I/O clock PLL. I/O clocking runs directly from
the 10–20 MHz clock input.
1.3.7 Interrupts
Flexible interrupts structure. Real-time interrupts can be
handled by a traditional interrupt service routine (ISR) or
individually assigned to independent threads.
1.3.8 Reset
The following sources are capable of causing a chip reset:
• Power-on
• Debug port
• Brownout
• Watchdog timer
• Parity error
• External reset
1.3.9 Programming and Debugging
The IP3023 device has advanced in-system programming
and debug support on-chip. This unobtrusive capability is
provided through an SPI interface. There is no need for a
bond-out chip for software development. This eliminates
concerns about differences in electrical characteristics
between a bond-out chip and the actual chip used in the
target application. Designers can test and revise code on
the same part used in the actual application.
Ubicom provides the complete Red Hat GNUPro tools,
including C compiler, assembler, linker, utilities and GNU
debugger. In addition, Ubicom offers an integrated
graphical development environment which includes an
editor, project manager, graphical user interface for the
GNU debugger, device programmer, and ipModule
configuration tool.
1.3.10 Other Supported Functions
• Random-number generator. The IP3023 includes an
on-chip hardware true random number generator. On-
chip random noise generates random bits which are
accumulated in a hardware 32-bit linear feedback
shift register (LFSR). This function can be used to
seed a software random number generator or to gen-
erate per-session cryptography keys.
• Boot through debug port from external flash. Unlike
the IP2000, there is no on-chip flash.
www.ubicom.com
5
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| PDF Descargar | [ Datasheet IP3023.PDF ] | |
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