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PDF DP83848I Data sheet ( Hoja de datos )
| Número de pieza | DP83848I | |
| Descripción | Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DP83848I (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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May 2008
DP83848I PHYTER® - Industrial Temperature
Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
Features
The DP83848I is a robust fully featured 10/100 single
port Physical Layer device offering low power con-
sumption, including several intelligent power down
states. These low power modes increase overall prod-
uct reliability due to decreased power dissipation. Sup-
porting multiple intelligent power modes allows the
application to use the absolute minimum amount of
power needed for operation. In addition to low power,
the DP83848I is optimized for cable length perfor-
mance far exceeding IEEE specifications.
• Low-power 3.3V, 0.18µm CMOS technology
• Low power consumption < 270mW Typical
• 3.3V MAC Interface
• Auto-MDIX for 10/100 Mb/s
• Energy Detection Mode
• 25 MHz clock out
• SNI Interface (configurable)
• RMII Rev. 1.2 Interface (configurable)
The DP83848I includes a 25MHz clock out. This • MII Serial Management Interface (MDC and MDIO)
means that the application can be designed with a
minimum of external parts, which in turn results in the
lowest possible total cost of the solution.
The DP83848I easily interfaces to twisted pair media
via an external transformer and fully supports JTAG
• IEEE 802.3u MII
• IEEE 802.3u Auto-Negotiation and Parallel Detection
• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
• IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE specification 1149.1 for ease of manufacturing.
Additionally both MII and RMII are supported ensuring
ease and flexibility of design.
• IEEE 1149.1 JTAG
• Integrated ANSI X3.263 compliant TP-PMD physical sub-
layer with adaptive equalization and Baseline Wander com-
The DP83848I features integrated sublayers to sup-
pensation
port both 10BASE-T and 100BASE-TX Ethernet proto-
cols, which ensures compatibility and interoperability
with all other standards based Ethernet solutions.
The DP83848I is offered in a small form factor (48 pin
LQFP) so that a minimum of board space is needed.
• Error-free Operation up to 150 meters
• Programmable LED support Link, 10 /100 Mb/s Mode, Activ-
ity, and Collision Detect
• Single register access for complete PHY status
• 10/100 Mb/s packet BIST (Built in Self Test)
Applications
• 48-pin LQFP package (7mm) x (7mm)
• High End Peripheral Devices
• Industrial Controls and Factory Automation
• General Embedded Applications
System Diagram
MPU/CPU
MII/RMII/SNI
DP83848I
10/100 Mb/s
25 MHz
Clock
Source
Status
LEDs
Typical Application
PHYTER® is a registered trademark of National Semiconductor.
© 2008 National Semiconductor Corporation
1
10BASE-T
or
100BASE-TX
www.national.com
1 page  
8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.2.28 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2.29 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2.30 100 Mb/s X1 to TX_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5 www.national.com
5 Page 
1.3 Clock Interface
Signal Name
X1
Type
I
X2
25MHz_OUT
O
O
1.4 LED Interface
See Table 3 for LED Mode Selection.
Pin #
34
33
25
Description
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock
reference input for the DP83848I and must be connected to a 25
MHz 0.005% (+50 ppm) clock source. The DP83848I supports ei-
ther an external crystal resonator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock refer-
ence input for the RMII mode and must be connected to a 50 MHz
0.005% (+50 ppm) CMOS-level oscillator source.
CRYSTAL OUTPUT: This pin is the primary clock reference out-
put to connect to an external 25 MHz crystal resonator device.
This pin must be left unconnected if an external CMOS oscillator
clock source is used.
25 MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25 MHz clock output to the sys-
tem.
In RMII mode, this pin provides a 50 MHz clock output to the sys-
tem.
This allows other devices to use the reference clock from the
DP83848I without requiring additional clock sources.
Signal Name
LED_LINK
LED_SPEED
LED_ACT/COL
Type
S, O, PU
S, O, PU
S, O, PU
Pin #
28
27
26
Description
LINK LED: In Mode 1, this pin indicates the status of the LINK.
The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit
and receive activity in addition to the status of the Link. The LED
will be ON when Link is good. It will blink when the transmitter or
receiver is active.
SPEED LED: The LED is ON when device is in 100 Mb/s and OFF
when in 10 Mb/s. Functionality of this LED is independent of mode
selected.
ACTIVITY LED: In Mode 1, this pin is the Activity LED which is
ON when activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indi-
cates Collision detection. For Mode 3, this LED output may be
programmed to indicate Full-duplex status instead of Collision.
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83848I.PDF ] | |
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