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Samsung Semiconductor - 2M x 32 Synchronous Mask ROM

Numéro de référence KM23SV64205T
Description 2M x 32 Synchronous Mask ROM
Fabricant Samsung Semiconductor 
Logo Samsung Semiconductor 





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KM23SV64205T fiche technique
KM23SV64205T
Advance Information
Synch. MROM
2Mx32 Synchronous MASKROM
FEATURES
GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
The KM23SV64205T is a synchronous high bandwidth mask
LVTTL compatible with multiplexed address
Address: Row address: RA0 ~ RA12
Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16)
Switchable organization
4,194,304 x 16(word mode) /
programmable ROM fabricated with SAMSUNGs high perfor-
mance CMOS process technology and is organized either as
4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double
word mode) depending on polarity of WORD pin.(see pin func-
2,097,152 x 32(double word mode)
tion description). Synchronous design allows precise cycle con-
All inputs are sampled at the rising edge of the system clock
trol, with the use of system clock, I/O transactions are possible
Read Performance at memory point of view
on every clock cycle. Range of operating frequencies, program-
@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)
@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
m@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
otSAC : 6ns
MRS cycle with address key programs
.c-. RAS Latency(1 & 2)
-. CAS Latency(3 ~ 6)
-. Burst Length : 4, 8
U-. Burst Type : Sequential & Interleaved
DQM for data-out masking
t4Package :86TSOP2 - 400
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part NO.
KM23SV64205T-10
KM23SV64205T-12
KM23SV64205T-15
KM23SV64205T-20
KM23SV64205T-30
MAX Freq.
100MHz
83MHz
66MHz
50MHz
33MHz
Interface
LVTTL
Package
86TSOP2
eeFUNCTIONAL BLOCK DIAGRAM
hQ0 Q16
ta. S. .Output Buffer
Q15 Q31
.DaCLK
wADD
ww t4U.comLCKE
LRAS
www.DataSheeCLK CKE
2M x 32
Cell Array
Column Decoder
Latency & Burst Length
LMR
LCAS
Timing Register
Programming Register
MR
RAS
CAS
CS
DQM
* Samsung Electronics reserves the right to
change products or specification without notice.

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