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PDF DS1204V Data sheet ( Hoja de datos )
| Número de pieza | DS1204V | |
| Descripción | Electronic Key | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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DS1204V
DS1204V
Electronic Key
PIN ASSIGNMENT
• Cannot be deciphered by reverse engineering
• Partitioned memory thwarts pirating
m• User-insertable packaging allows personal posses-
sion
o• Exclusive blank keys on request
.c• Appropriate identification can be made with a 64-bit
reprogrammable memory
U• Unreadable 64-bit security match code virtually pre-
vents deciphering by exhaustive search with over
1019 possibilities
t4• 128 bits of secure read/write memory create addition-
al barriers by permitting data changes as often as
eneeded
e• Rapid erasure of identification security match code
and secure read/write memory can occur if tampering
his detected
• Low-power CMOS circuitry
S• Four million bps data rate
ta• Durable and rugged
• Applications include software authorization, gray
amarket software protection, proprietary data, financial
transactions, secure personnel areas, and system ac-
cess control
.DDESCRIPTION
The DS1204V Electronic Key is a miniature security
wsystem that stores 64 bits of user-definable identifica-
tion code and a 64-bit security match code that protects
w128 bits of read/write nonvolatile memory. The 64-bit
identification code and the security match code are pro-
grammed into the key via a special program mode oper-
wation. After programming, the key follows a procedure
mwith a serial format to retrieve or update data. Interface
ocost to a microprocessor is minimized by on-chip circuit-
.cry that permits data transfer with only three signals:
UClock (CLK), Reset (RST), and Data Input/Output (DQ).
DALLAS
DS1204V
ELECTRONIC KEY
SIDE
15
BOTTOM: PIN VIEW
1.0 IN
See Mech. Drawings
Section
PIN DESCRIPTION
Pin 1 - VCC
Pin 2 - RST
Pin 3 - DQ
Pin 4 - CLK
Pin 5 - GND
+5 Volts
Reset
Data Input/Output
Clock
Ground
Low pin count and a guided entry for mating receptacle
overcome mechanical problems normally encountered
with conventional integrated circuit packaging, making
the device transportable and user-insertable.
OPERATION – NORMAL MODE
The Electronic Key has two modes of operation: normal
and program. The block diagram (see Figure 1) illus-
trates the main elements of the key when used in the
normal mode. To initiate data transfer with the key, RST
is taken high and 24 bits are loaded into the command
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1 page  
FLOW CHART - PROGRAM MODE Figure 6
RESET HIGH
WRITE COMMAND PROTOCOL
NO MATCH
PROGRAM MODE
DS1204V
WRITE 64 BITS IDENTIFICATION
WRITE 64 BITS SECURITY MATCH
STOP
RESET LOW
OUTPUT IN HIGH Z
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves three functions. First, it turns
on control logic, which allows access to the command
register for the command sequence. Second, the RST
signal provides a power source for the cycle to follow. To
meet this requirement, a drive source for RST of 2 mA @
3.5 volts is required. However, if the VCC pin is con-
nected to a 5-volt source within nominal limits, the RST
is not used as a source of power and input levels revert
to normal VIH and VIL inputs with a drive current require-
ment of 500 µA. Third, the RST signal provides a meth-
od of terminating data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, the data must be valid
during the rising edge of a clock cycle. Command bits
and data bits are input on the rising edge of the clock and
data bits are output on the falling edge of the clock. The
rising edge of the clock returns the DQ pin to a high im-
pedance state. All data transfer terminates if the RST
pin is low and the DQ pin goes to a high impedance
state. When data transfer to the key is terminated using
RST, the transition of RST must occur while the clock is
at a high level to avoid disturbing the last bit of data. Data
transfer is illustrated in Figure 8 for normal mode and
Figure 9 for program mode.
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DS1204V.PDF ] | |
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