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Intel - PCI-to-PCI Bridge

Numéro de référence FW21555
Description PCI-to-PCI Bridge
Fabricant Intel 
Logo Intel 





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FW21555 fiche technique
taSh2Be1er5itd45Ug5.ecNomon-Transparent PCI-to-PCIDatasheet
ww.Da Product Featuress Full compliance with the PCI local Bus
w Specification, Revision 2.2, plus:
m—PCI Power Management support
— Vital Product Data (VPD) support
o—CompactPCI Distributed Hot-Swap
.csupport
s 3.3-V operation with 5.0-V tolerant I/O
s Selectable asynchronous or synchronous
Uprimary and secondary interface clocks
t4s Concurrent primary and secondary bus
operation
s Fully compliant with the Advanced
eConfiguration Power Interface (ACPI)
specification
es Fully compliant with the PCI Bus Power
Management specification
hs Queuing of multiple transactions in either
direction
Ss 256 bytes of posted write (data and
taaddress) buffering in each direction
s 256 bytes of read data buffering in each
direction
as Four delayed transaction entries in each
direction
.Ds Two dedicated I2O delayed transaction
entries
s Two sets of standard PCI Configuration
wregisters corresponding to the primary and
secondary interface; each set is accessible
from either the primary or secondary
winterface
ms Direct offset address translation for
w odownstream memory and I/O transactions
.cs Hardware enable for secondary bus central
functions
t4Us IEEE Standard 1149.1 boundary-scan
JTAG interface
s Four primary interface base address
configuration registers for downstream
forwarding, with size and prefetchability
programmable for all four address ranges
s Three secondary interface address
configuration registers specifying local
address ranges for upstream forwarding,
with size and prefetchability programmable
for all three address ranges
s Inverse decoding above the 4 GB address
boundary for upstream DACs
s Ability to generate Type 0 and Type 1
configuration commands on the primary or
secondary interface via configuration or I/O
CSR accesses
s Ability to generate I/O commands on the
primary or secondary interface via I/O CSR
accesses
s I2O message unit
s Doorbell registers for software generation
of primary and secondary bus interrupts, 16
bits per interface
s Eight Dwords of scratchpad registers
s Generic own bit (can memory-map)
semaphore
s Parallel flash ROM interface with primary
bus expansion ROM base address register
s Serial ROM interface
s Secondary bus arbiter support for up to
nine external devices at 33 MHz and up to
four external devices at 66 MHz (in
addition to the 21555)
s Secondary bus clock output for
synchronous operation
s Four 32-bit base address configuration
registers mapping the 21555 control and
status registers (CSRs)
s Available in 33 MHz and 66 MHz versions
heeNotice: This document contains preliminary information on new products in production. The
Sspecifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
www.DataOrder Number: 278320-002

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