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PDF DS18B20-PAR Data sheet ( Hoja de datos )
| Número de pieza | DS18B20-PAR | |
| Descripción | 1-Wire Parasite-Power Digital Thermometer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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ShFEATURES
ta• Unique 1-wire interface requires only one
aport pin for communication
.D• Derives power from data line (“parasite
wpower”)—does not need a local power supply
ww• Multi-drop capability simplifies distributed
temperature sensing applications
m• Requires no external components
o• ±0.5°C accuracy from –10°C to +85°C
.c• Measures temperatures from –55°C to
+100°C (–67°F to +212°F)
• Thermometer resolution is user-selectable
Ufrom 9 to 12 bits
t4• Converts temperature to 12-bit digital word in
750 ms (max.)
e• User–definable non-volatile temperature
alarm settings
e• Alarm search command identifies and
haddresses devices whose temperature is
outside of programmed limits (temperature
Salarm condition)
ta• Software compatible with the DS1822-PAR
• Ideal for use in remote sensing applications
a(e.g., temperature probes) that do not have a
w.Dlocal power source
DS18B20-PAR
1-Wire® Parasite-Power
Digital Thermometer
PIN ASSIGNMENT
DALLAS
18B20P
123
123
(BOTTOM VIEW)
TO-92
(DS18B20-PAR)
PIN DESCRIPTION
GND - Ground
DQ - Data In/Out
NC - No Connect
wDESCRIPTION
The DS18B20-PAR digital thermometer provides 9 to 12–bit centigrade temperature measurements and
w omhas an alarm function with nonvolatile user-programmable upper and lower trigger points. The
.cDS18B20-PAR does not need an external power supply because it derives power directly from the data
Uline (“parasite power”). The DS18B20-PAR communicates over a 1-wire bus, which by definition
t4requires only one data line (and ground) for communication with a central microprocessor. It has an
eoperating temperature range of –55°C to +100°C and is accurate to ±0.5°C over a range of –10°C to
e+85°C.
ShEach DS18B20-PAR has a unique 64-bit identification code, which allows multiple DS18B20-PARs to
tafunction on the same 1–wire bus; thus, it is simple to use one microprocessor to control many DS18B20-
aPARs distributed over a large area. Applications that can benefit from this feature include HVAC
.Denvironmental controls, temperature monitoring systems inside buildings, equipment or machinery, and
process monitoring and control systems.
www1 of 19
043001
1 page  
DS18B20-PAR
The master device can check the alarm flag status of all DS DS18B20-PARs on the bus by issuing an
Alarm Search [ECh] command. Any DS18B20-PARs with a set alarm flag will respond to the command,
so the master can determine exactly which DS18B20-PARs have experienced an alarm condition. If an
alarm condition exists and the TH or TL settings have changed, another temperature conversion should be
done to validate the alarm condition.
64-BIT LASERED ROM CODE
Each DS18B20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8
bits of the ROM code contain the DS18B20-PAR’s 1–wire family code: 28h. The next 48 bits contain a
unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is
calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in
the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic
allow the DS18B20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS
SYSTEM section of this datasheet.
64-BIT LASERED ROM CODE Figure 5
8-BIT CRC
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE (28h)
MSB
LSB MSB
LSB MSB
LSB
MEMORY
The DS18B20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL)
and configuration register. Note that if the DS18B20-PAR alarm function is not used, the TH and TL
registers can serve as general-purpose memory. All memory commands are described in detail in the
DS18B20-PAR FUNCTION COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4
contains the configuration register data, which is explained in detail in the CONFIGURATION
REGISTER section of this datasheet. Bytes 5, 6 and 7 are reserved for internal use by the device and
cannot be overwritten; these bytes will return all 1s when read.
Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0
through 7 of the scratchpad. The DS18B20-PAR generates this CRC using the method described in the
CRC GENERATION section.
Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command, and the
data must be transmitted to the DS18B20-PAR starting with the least significant bit of byte 2. To verify
data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-wire bus starting with the least
significant bit of byte 0. To transfer the TH, TL and configuration data from the scratchpad to EEPROM,
the master must issue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM
to the scratchpad at any time using the Recall E2 [B8h] command. The master can issue “read time slots”
(see the 1-WIRE BUS SYSTEM section) following the Recall E2 command and the DS18B20-PAR will
indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is
done.
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5 Page 
ROM COMMANDS FLOW CHART Figure 10
DS18B20-PAR
Initialization
Sequence
MASTER TX
RESET PULSE
DS18B20-PAR
TX PRESENCE
PULSE
MASTER TX ROM
COMMAND
33h
READ ROM
COMMAND
N
Y
DS18B20-PAR TX
FAMILY CODE
1 BYTE
DS18B20-PAR TX
SERIAL NUMBER
6 BYTES
DS18B20-PAR TX
CRC BYTE
55h
MATCH ROM
COMMAND
N
Y
MASTER TX
BIT 0
F0h
SEARCH ROM
COMMAND
N
Y
ECh
N
ALARM SEARCH
COMMAND
Y
DS18B20-PAR TX BIT 0
DS18B20-PAR TX BIT 0
MASTER TX BIT 0
DS18B20-PAR TX BIT 0
DS18B20-PAR TX BIT 0
MASTER TX BIT 0
CCh
SKIP ROM
COMMAND
N
Y
BIT 0
MATCH?
N
Y
N
BIT 0
MATCH?
Y
MASTER TX
BIT 1
DS18B20-PAR TX BIT 1
DS18B20-PAR TX BIT 1
MASTER TX BIT 1
DEVICE(S)
WITH ALARM
FLAG SET?
N
Y
BIT 1
MATCH?
N
Y
MASTER TX
BIT 63
BIT 63
MATCH?
N
Y
N
BIT 1
MATCH?
Y
DS18B20-PAR TX BIT 63
DS18B20-PAR TX BIT 63
MASTER TX BIT 63
N
BIT 63
MATCH?
Y
MASTER TX
FUNCTION
COMMAND
(FIGURE 11)
11 of 19
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