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PDF TC220E Data sheet ( Hoja de datos )
| Número de pieza | TC220E | |
| Descripción | (TC220C/E) DRAM Core | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC220E (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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TOSHIBAet4U.com TC220C/E DRAM Core0.3µm 3T dRAMASIC
SheToshiba’s 1 Mbit embedded DRAM core is available for the
ta Embedded DRAM BenefitsTC220C and TC220E product families. Each DRAM cell is based
aon a three transistor structure as shown in Figure 1. This multi-fea-
ture DRAM core is easily integrated into a broad range of appli-
.Dcations through utilization of different core configurations.
wDwRwAM Core Features m• Power supply: 3.3V ±0.3V
• Memory configurations
o– 128K x 8 bit
.c– 64K x 16 bit
– 32K x 32 bit
Target AppU– 16K x 64 bit
lications• Full address without multiplex
t4• Separate data input and output
• Read access modes
e– Random access
e– EDO/Hyper page mode
• Refresh scheme
h– RAS only refresh
S– CBR (CAS before RAS) refresh
• Performance specification
ta– trc random read cycle: 50 ns
– tpc page mode read cycle: 25 ns
a– Refresh cycle: 256 cycles/ms (@Tj = 85°C)
Benefits derived from integration of DRAM with logic are:
• Flexibility in utilizing different DRAM core configurations
based on the application requirement
• Memory access time lower than discrete packaged devices
• Elimination of a large number of pins and associated packages,
effectively reducing circuit board area
• Lower power consumption since systems with fast and wide
memory busses will dissipate significantly less power due to
lower capacitance on-chip connections
• Lower switching noise on data bus between memory and logic
Applications for 3T dRAMASIC™ include hard disk drive con-
trollers, buffer memory for hubs and switches and printers.
www.D mRead word
taSheet4U.coWrite word
aWrite bit
www.DFigure 1. Three-Transistor DRAM Cell
OE
WE
RAS
CAS
A0–A7
A8–A15
O0–O15
I0–I15
Output Buffer
Add. Counter (CBR)
Input Buffer
Clock
Generator
Column
Address
Buffer
Row
Address
Buffer
Column Decoder
Sense Amplifiers
Memory Cell Array
4569-02
Figure 2. DRAM Core Block Diagram
Product Brief
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
1
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet TC220E.PDF ] | |
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