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PDF PCI6254 Data sheet ( Hoja de datos )
| Número de pieza | PCI6254 | |
| Descripción | Dual Mode PCI to PCI Bridge | |
| Fabricantes | PLX Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PCI6254 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
.comPCI 6254 (HB6)
Dual Mode
t4UUniversal PCI-to-PCI Bridge
eData Book
www.DataShe www.DataSheet4U.com
1 page  
PCI 6254 Dual-Mode Universal PCI-to-PCI Bridge
Adaptive High Performance Asynchronous 66MHz 64-bit PCI-to-PCI Bridge for
Servers, Storage, Telecommunication, Networking and Embedded Applications
PLX’s latest PCI 6254 64-bit PCI-to-PCI bridge is designed for high performance, high availability applications in
bus expansions, programmable data transfer rate control, frequency conversions from slower PCI to faster PCI or
from faster PCI to slower PCI buses, address remapping, high availability Hot Swap enabling and universal
system-to-system bridging. PCI 6254 has sophisticated buffer management and buffer configuration options
designed to provide customizable performance optimization.
• PCI Local Bus Specification Rev 2.3 support
• High speed PCI buffer supports 3.3V signaling with
5V input signal tolerance
• CPCI Hot Swap Specification PICMG 2.1 R2.0 with
PI = 1 support
• Device Hiding support eliminates mid-transaction
extraction problems
• Programmable 32 bit to 64 bit access conversion.
• Programmable Address Translation to Secondary Bus
• Flow-Through 0 wait state burst up to 4K bytes for
optimal large volume data transfer
• Supports up to 4 simultaneous posted write
transactions and 4 simultaneous Delayed transactions
in each direction
• Provides 1K Bytes of buffering
256 byte upstream posted write buffer
256 byte downstream posted write buffer
256 byte upstream read data buffer
256 byte downstream read data buffer
• Programmable prefetch amount of up to 256 bytes for
maximum read performance optimization
• Supports out of order delayed transactions
• Support Secondary Port PCI Private Memory Space
• Option to eliminates possible dead lock on PCI-VME
bridges before or behind PCI 6254
• Serial EEPROM loadable and programmable PCI
READ ONLY Register configurations.
• External arbiter or programmable arbitration for 9 bus
masters on secondary interface support
• 10 Secondary clock outputs with pin controlled enable
and individual maskable control
• PCI Mobile Design Guide and Power Management D3
Cold Wakeup capable with PME# support
• 16 GPIO pins with output control and 8 are with
power up status latch capabilities
• Enhanced address decoding
Support 32-bit I/O address range
32-bit memory-mapped I/O address range
ISA aware mode for legacy support in the first
64KB of I/O address range
VGA addressing and palette snooping support
• Provides an IEEE standard 1149.1 JTAG interface for
boundary scan test
• Asynchronous design supports standard 66Mhz to
33MHz and faster secondary port speed such as
33Mhz to 66MHz conversion
• PCI 6254 package ball layout is super set of PLX PCI
6154 and Intel 21154 when operating in Transparent
Mode
• Industry standard 31mm x 31mm 365-ball PBGA
package
PCI 6254 Non-Transparent and Universal Mode Features
• Programmable Transparent, Non-Transparent or Universal Mode operation
• Jumper less switching between System and Peripheral Slot applications in CPCI
• Programmable Primary or Secondary Port System boot up priority.
• Semaphore backed Cross-bridge Configuration Space access
• Powerful multi-source (Direct encoded, door bell, PCI Reset, external pin) programmable interrupts
• Message Interrupt Support
• Optional power up 16M memory space claim to avoid Initially Retry or Initially Not Respond requirement
• Behave as a Memory mapped PCI device
• Primary and Secondary Port controllable GPIOs
• Power-Good input
• Available Primary and Secondary Power Status inputs for port power detection
• Independent Primary and Secondary Port Reset inputs
• Configurable Primary and Secondary Reset Outputs
• Sticky user registers immune to PCI resets
• Supporting up to 9 secondary PCI master devices
PCI 6254 Data Book v2.1
2003 PLX Technology, Inc. All rights reserved.
5
5 Page 
11.2
11.3
ACQUIRING EXCLUSIVE ACCESS ACROSS PCI 6254.................................................................................... 107
ENDING EXCLUSIVE ACCESS ...................................................................................................................... 108
12 PCI BUS ARBITRATION ............................................................................................................................ 109
12.1 PRIMARY PCI BUS ARBITRATION ................................................................................................................ 109
12.2 SECONDARY PCI BUS ARBITRATION ........................................................................................................... 109
12.2.1 Secondary Bus Arbitration Using the Internal Arbiter....................................................................... 109
12.2.1.1
Rotating Priority Scheme................................................................................................................................ 110
12.2.1.2
Fixed Priority Scheme .................................................................................................................................... 111
12.2.2 Secondary Bus Arbitration using an External Arbiter ....................................................................... 111
12.2.3 Internal Arbitration Parking............................................................................................................... 111
13 GENERAL PURPOSE I/O INTERFACE..................................................................................................... 112
13.1 GPIO CONTROL REGISTERS ...................................................................................................................... 113
14 CLOCKS ..................................................................................................................................................... 114
14.1 PRIMARY AND SECONDARY CLOCK INPUTS.................................................................................................. 114
14.2 SECONDARY CLOCK OUTPUTS.................................................................................................................... 114
14.3 DISABLING UNUSED SECONDARY CLOCK OUTPUTS ..................................................................................... 114
14.3.1 Secondary Clock Control.................................................................................................................. 115
14.3.2 Force S_CLK[9:0] to LOW................................................................................................................ 115
14.4 USING AN EXTERNAL CLOCK SOURCE......................................................................................................... 116
14.5 FREQUENCY DIVISION OPTIONS.................................................................................................................. 116
14.6 RUNNING SECONDARY PORT FASTER THAN PRIMARY PORT......................................................................... 116
14.7 UNIVERSAL MODE CLOCK BEHAVIOR .......................................................................................................... 116
15 FREQUENCY OPERATION ....................................................................................................................... 117
15.1 66-MHZ OPERATION.................................................................................................................................. 117
16 RESET ........................................................................................................................................................ 118
16.1 POWER GOOD RESET ................................................................................................................................ 118
16.1.1 PWRGD and Output Signals ............................................................................................................ 118
16.2 PRIMARY RESET INPUT............................................................................................................................... 119
16.3 PRIMARY RESET OUTPUT ........................................................................................................................... 119
16.4 SECONDARY RESET INPUT ......................................................................................................................... 120
16.4.1 Universal Mode Secondary Reset Input........................................................................................... 120
16.5 SECONDARY RESET OUTPUT...................................................................................................................... 120
16.6 SOFTWARE CHIP RESET............................................................................................................................. 121
16.7 POWER MANAGEMENT INTERNAL RESET ..................................................................................................... 121
16.8 RESET TO FIRST CYCLE ACCESS LATENCY.................................................................................................. 121
16.9 RESET INPUTS TABLE................................................................................................................................. 122
16.10
POWER UP AND RESET PIN STATE TABLE ............................................................................................... 123
16.10.1
PCI 6254 Rev AA Power Up and Reset Pin State Table ............................................................. 125
17 BRIDGE BEHAVIOR .................................................................................................................................. 127
17.1 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ........................................................................... 127
17.1.1 Master Abort ..................................................................................................................................... 127
17.2 PARITY AND ERROR REPORTING................................................................................................................. 127
17.2.1 Reporting Parity Errors..................................................................................................................... 128
17.3 SECONDARY IDSEL MAPPING.................................................................................................................... 128
17.4 32-BIT TO 64-BIT CYCLE CONVERSION ........................................................................................................ 128
PCI 6254 Data Book v2.1
2003 PLX Technology, Inc. All rights reserved.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCI6254.PDF ] | |
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