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PDF UPD44165084 Data sheet ( Hoja de datos )
| Número de pieza | UPD44165084 | |
| Descripción | (UPD44165084/184/364) 18M-BIT QDRII SRAM 4-WORD BURST OPERATION | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44165084, 44165184, 44165364
18M-BIT QDRTMII SRAM
4-WORD BURST OPERATION
Description
The µPD44165084 is a 2,097,152-word by 8-bit, the µPD44165184 is a 1,048,576-word by 18-bit and the
µPD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The µPD44165084, µPD44165184 and µPD44165364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply and HSTL I/O
• DLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Four-tick burst for reduced address frequency
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15825EJ7V1DS00 (7th edition)
Date Published July 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001
1 page  
µPD44165084, 44165184, 44165364
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44165364F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ VSS NC
/W /BW2 /K /BW1 /R
NC VSS CQ
B Q27 Q18 D18
A /BW3 K /BW0 A
D17 Q17
Q8
C D27 Q28 D19
VSS
A
NC
A
VSS D16 Q7
D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29
D29
Q20 VDDQ
VSS
VSS
VSS VDDQ Q15
D6
Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30
D22
Q22 VDDQ
VDD
VSS
VDD VDDQ Q13 D13
D5
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4
D4
K Q32
D32
Q23 VDDQ
VDD
VSS
VDD VDDQ Q12
D3
Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
D2
N D34 D26 Q25 VSS
A
A
A VSS Q10 D9 D1
P Q35 D35 Q26
A
A
C
A
A Q9 D0 Q0
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A
D0 to D35
Q0 to Q35
/R
/W
/BW0 to /BW3
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
Remark Refer to Package Drawing for the index mark.
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Data Sheet M15825EJ7V1DS
5
5 Page 
Electrical Specifications
µPD44165084, 44165184, 44165364
Absolute Maximum Ratings
Parameter
Supply voltage
Output supply voltage
Input voltage
Input / Output voltage
Operating ambient temperature
Storage temperature
Symbol Conditions
VDD
VDDQ
VIN
VI/O
TA
Tstg
MIN.
–0.5
–0.5
–0.5
–0.5
0
–55
TYP.
MAX.
+2.9
VDD
VDD + 0.5 (2.9 V MAX.)
VDDQ + 0.5 (2.9 V MAX.)
70
+125
Unit
V
V
V
V
°C
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit Note
Supply voltage
VDD 1.7 1.9 V
Output supply voltage
VDDQ
1.4
VDD
V1
High level input voltage
VIH (DC)
VREF + 0.1
VDDQ + 0.3 V
1, 2
Low level input voltage
VIL (DC)
–0.3
VREF – 0.1 V 1, 2
Clock input voltage
VIN
–0.3
VDDQ + 0.3 V
1, 2
Reference voltage
VREF
0.68
0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit Note
High level input voltage
VIH (AC)
VREF + 0.2
– V1
Low level input voltage
VIL (AC)
–
VREF – 0.2
V
1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Data Sheet M15825EJ7V1DS
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD44165084.PDF ] | |
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