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PDF XCR5128C Data sheet ( Hoja de datos )
| Número de pieza | XCR5128C | |
| Descripción | 128 Macrocell CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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APPLICATION NOTE
0
XCR5128C: 128 MacrocellR
U.com CPLD with Enhanced ClockingDS042 (v1.2) August 10, 2000
0 14* Product Specification
et4Features
he• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
S• Fast Zero Power (FZP™) design technique provides
taultra-low power and very high speed
a m• 5V, In-System Programmable (ISP) using a JTAG
.Dinterface
w o- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
ww .cVerify
- Supported by multiple ISP programming platforms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
U- JTAG commands include: Bypass, Idcode
• High speed pin-to-pin delays of 7.5 ns
t4• Ultra-low static power of less than 100 µA
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
e• Deterministic timing model that is extremely simple to
use
e• Up to 20 clocks available
• Support for complex asynchronous clocking
h• Innovative XPLA™ architecture combines high speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
S• 20 years data retention guaranteed
• Logic expandable to 37 product terms
ta• PCI compliant
• Advanced 0.5µ E2CMOS process
a• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
.D• Reprogrammable using industry standard device
mprogrammers
o• Innovative Control Term structure provides either sum
w .cterms or product terms in each logic block for:
U- Programmable 3-state buffer
w t4- Asynchronous macrocell register preset/reset
- Up to two asynchronous clocks
e• Programmable global 3-state pin facilitates `bed of nails'
etesting without using logic resources
w h• Available in TQFP and LQFP packages
www.DataS• Available in both Commercial and Industrial grades
Description
The XCR5128C CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner® family of CPLDs
from Xilinx. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design tech-
nique, the XCR5128C offers true pin-to-pin speeds of 7.5
ns, while simultaneously delivering power that is less than
100 µA at standby without the need for “turbo bits” or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR5128C CPLDs are supported by industry stan-
dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses Xilinx developed tools including WebFITTER.
The XCR5128C CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
DS042 (v1.2) August 10, 2000
www.xilinx.com
1
1-800-255-7778
1 page  
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
R
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner XCR5128C. The macrocell can be config-
ured as either a D- or T-type flip-flop or a combinatorial logic
function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. Four of the clock sources (CLK0, CLK1,
CLK2, CLK3) are connected to low-skew, device-wide clock
networks designed to preserve the integrity of the clock sig-
nal by reducing skew between rising and falling edges.
Clock 0 (CLK0) is designated as a “synchronous” clock and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as “syn-
chronous” clocks that are driven by an external source, or
as “asynchronous” clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2 and CLK3 can clock the mac-
rocell flip-flops on either the rising edge or the falling edge
of the clock signal. The other clock sources are two of the
six control terms (CT2 and CT3) provided in each logic
block. These clocks can be individually configured as either
a PRODUCT term or SUM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
tCO time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the tSU time is reduced.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buffers in each macrocell. Con-
trol terms CT0 and CT1 are used to control the asynchro-
nous Preset/Reset of the macrocell's flip-flop. Note that the
Power-on Reset leaves all macrocells in the “zero” state
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell's output buffer. Control terms CT4 and CT5 can
be used to control the Output Enable of the macrocell's out-
put buffer. Having four dedicated Output Enable control
terms ensures that the CoolRunner devices are PCI com-
pliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-State (GTS) pin, which, when enabled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support “In-Circuit Testing” or “Bed-of-Nails
Testing”.
There are two feedback paths to the ZIA: one from the mac-
rocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an out-
put, the output buffer is enabled, and the macrocell feed-
back path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (See
the section on terminations in this data sheet and the appli-
cation note Terminating Unused I/O Pins in Xilinx XPLA1
and XPLA2 CoolRunner CPLDs).
TO ZIA
PAL
PLA
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
D/T Q
INIT
(P or R)
GTS
CT0
CT1
GND
GND
Figure 3: XCR5128C Macrocell Architecture
5 www.xilinx.com
1-800-255-7778
SP00558
DS042 (v1.2) August 10, 2000
5 Page 
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
Absolute Maximum Ratings 1
R
Symbol
Parameter
Min.
Max.
Unit
VCC Supply voltage2
-0.5 7.0
V
VI Input voltage
-1.2 VCC +0.5
V
VOUT
Output voltage
-0.5 VCC +0.5
V
IIN Input current
-30 30 mA
IOUT
Output current
-100
100
mA
TJ Maximum junction temperature
-40 150 °C
Tstr Storage temperature
-65 150 °C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70°C
-40 to +85°C
Voltage
5.0V +5%
5.0V +10%
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VIL Input voltage low
VCC = 4.75V
0.8 V
VIH Input voltage high
VCC = 5.25V
2.0 V
VI Input clamp voltage
VCC = 4.75V, IIN = -18 mA
-1.2 V
VOL Output voltage low
VCC = 4.75V, IOL = 12 mA
0.5 V
VOH Output voltage high
VCC = 4.75V, IOH = -12 mA
2.4
V
II Input leakage current
VIN = 0 to VCC
-10 10 µA
IOZ
ICCQ1
ICCD1, 2
3-stated output leakage current
Standby current
Dynamic current
VIN = 0 to VCC
VCC = 5.25V, TAMB = 0°C
VCC = 5.25V, TAMB = 0°C at 1 MHz
-10 10 µA
100 µA
3 mA
VCC = 5.25V, TAMB = 0°C at 50 MHz
75 mA
IOS
Short circuit output current3
One pin at a time for no longer than 1
-50
-200
mA
second
CIN
CCLK
CI/O
Input pin capacitance3
Clock input capacitance3
I/O pin capacitance3
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
8 pF
5 12 pF
10 pF
Notes:
1. See Table 1 on page 7 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
11
www.xilinx.com
DS042 (v1.2) August 10, 2000
1-800-255-7778
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet XCR5128C.PDF ] | |
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