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PDF FT245BQ Data sheet ( Hoja de datos )
| Número de pieza | FT245BQ | |
| Descripción | USB FIFO IC | |
| Fabricantes | Future Technology Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FT245BQ (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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.com FT245BQ USB FIFO ( USB - Parallel ) I.C.
heet4UThe FT245BQ is the lead free version of the 2nd generation of FTDI’s popular USB FIFO I.C. This device not only
taSadds extra functionality to its FT8U245AM predecessor and reduces external component count, but also maintains a
ahigh degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as
.Dincreasing the potential for using the device in new application areas.
w1.0 Features
wwHARDWARE FEATURES
• UHCI / OHCI / EHCI host controller compatible
• Single Chip USB Parallel FIFO bi-directional
• USB 1.1 and USB 2.0 compatible
Data Transfer
• USB VID, PID , Serial Number and Product
m• Transfer Data rate to 1M Byte / Sec - D2XX Drivers
Description strings in external EEPROM
o• Transfer Data rate to 300 Kilobyte / Sec - VCP
• EEPROM programmable on-board via USB
.cDrivers
• Compact 5 x 5 mm Lead free RoHS compliant
• Simple to interface to MCU / PLD/ FPGA logic with
QFN32 package
Ua 4 wire handshake interface
VIRTUAL COM PORT (VCP) DRIVERS for
• Entire USB protocol handled on-chip… no USB-
- Windows 98 and Windows 98 SE
t4specific firmware programming required
- Windows 2000 / ME / XP
e• FTDI’s royalty-free VCP and D2XX drivers
- Windows CE 4.2
eliminate the requirement for USB driver
- MAC OS-8 and OS-9
edevelopment in most cases.
- MAC OS-X
h• 384 Byte FIFO Tx buffer / 128 Byte FIFO Rx Buffer - Linux 2.40 and greater
Sfor high data throughput.
D2XX (USB Direct Drivers + DLL S/W Interface)
• New Send Immediate support via SI Pin for
- Windows 98 and Windows 98 SE
taoptimised data throughput.
- Windows 2000 / ME / XP
a• Support for USB Suspend / Resume through
- Windows CE 4.2
PWREN# and WAKEUP pins.
- Linux 2.4 and Greater
.D• Support for high power USB Bus powered devices APPLICATION AREAS
through PWREN# pin
- Easy MCU / PLD / FPGA interface to USB
w• Adjustable RX buffer timeout
- Upgrading Legacy Peripheral Designs to USB
• In-built support for event characters
- USB Instrumentation
w• Integrated level converter on FIFO and control
- USB Industrial Control
wsignals for interfacing to 5V and 3.3V logic
- USB Audio and Low Bandwidth Video data transfer
• Integrated 3.3V regulator for USB IO
- PDA USB data transfer
om• Integrated Power-On-Reset circuit
- USB MP3 Player Interface
.c• Integrated 6MHz – 48Mhz clock multiplier PLL
- USB FLASH Card Reader / Writers
U• USB Bulk or Isochronous data transfer modes
- Set Top Box (S.T.B.) PC - USB interface
et4• New Bit-Bang Mode allows the data bus to be used - USB Digital Camera Interface
eas an 8 bit general purpose IO Port without the
- USB Hardware Modems
Shneed for MCU or other support logic.
- USB Wireless Modems
ta• 4.35V to 5.25V single supply operation
www.DaDS245BQ Version 1.6 © Future Technology Devices Intl. Ltd. 2005
Page 1 of 24
1 page  
3.0 Block Diagram ( simplified )
VCC
3V3OUT
3.3 Volt
LDO
Regulator
USBDP
USBDM
USB
Transceiver
Serial Interface
Engine
( SIE )
USB DPLL
FT245BQ USB FIFO ( USB - Parallel ) I.C.
Send Immediate / WakeUP
PWREN#
FIFO Receive
Buffer
128 Bytes
USB
Protocol Engine
FIFO
Controller
FIFO Transmit
Buffer
384 Bytes
D0
D1
D2
D3
D4
D5
D6
D7
RD#
WR
RXF#
TXE#
XTOUT
XTIN
GND
TEST
6MHZ
Oscillator
x8 Clock
Multiplier
48MHz
12MHz
RESET#
3V3OUT
RESET
GENERATOR
EEPROM
Interface
EECS
EESK
EEDATA
RSTOUT#
3.1 Functional Block Descriptions
• 3.3V LDO Regulator
• USB DPLL
The 3.3V LDO Regulator generates the 3.3 volt
The USB DPLL cell locks on to the incoming NRZI
reference voltage for driving the USB transceiver
USB data and provides separate recovered clock
cell output buffers. It requires an external
and data signals to the SIE block.
decoupling capacitor to be attached to the 3V3OUT
regulator output pin. It also provides 3.3V power to • 6MHz Oscillator
the RSTOUT# pin. The main function of this block
The 6MHz Oscillator cell generates a 6MHz
is to power the USB Transceiver and the Reset
reference clock input to the x8 Clock multiplier from
Generator Cells rather than to power external logic.
an external 6MHz crystal or ceramic resonator.
However, external circuitry requiring 3.3V nominal
at a current of not greater than 5mA could also
• x8 Clock Multiplier
draw its power from the 3V3OUT pin if required.
The x8 Clock Multiplier takes the 6MHz input
from the Oscillator cell and generates a 12MHz
• USB Transceiver
reference clock for the SIE, USB Protocol Engine
The USB Transceiver Cell provides the USB 1.1 /
and FIFO controller blocks. It also generates a
USB 2.0 full-speed physical interface to the USB
48MHz reference clock for the USB DPLL.
cable. The output drivers provide 3.3 volt level slew
rate control signalling, whilst a differential receiver
and two single ended receivers provide USB data
in, SEO and USB Reset condition detection.
DS245BQ Version 1.6 © Future Technology Devices Intl. Ltd. 2005
Page 5 of 24
5 Page 
FT245BQ TIMING DIAGRAM – FIFO READ CYCLE
RXF#
FT245BQ USB FIFO ( USB - Parallel ) I.C.
T6
T5
RD#
T1 T2
D0..D7
T3 T4
valid data
Time
T1
T2
T3
T4
T5
T6
Description
Min Max Unit
RD Active Pulse Width
50 ns
RD to RD Pre-Charge Time
50 + T6
ns
RD Active to Valid Data *** Note 4
20 50 ns
Valid Data Hold Time from RD Inactive *** Note 4 0
ns
RD Inactive to RXF#
0 25 ns
RXF inactive after RD cycle
80 ns
*** Note 4 - Load 30 pF
FT245BQ TIMING DIAGRAM – FIFO WRITE CYCLE
T12
T11
TXE#
T7 T8
WR
D0..D7
T10
T9
valid data
Time Description
Min Max Unit
T7 WR Active Pulse Width
50 ns
T8 WR to WR Pre-Charge Time
50
ns
T9 Data Setup Time before WR inactive
20
ns
T10 Data Hold Time from WR inactive
0
ns
T11 WR Inactive to TXE#
5 25 ns
T12 TXE inactive after WR cycle
80
ns
DS245BQ Version 1.6 © Future Technology Devices Intl. Ltd. 2005
Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet FT245BQ.PDF ] | |
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