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PDF PE3503 Data sheet ( Hoja de datos )

Número de pieza PE3503
Descripción Low Power CMOS Divide by 8 Prescaler
Fabricantes Peregrine Semiconductor 
Logotipo Peregrine Semiconductor Logotipo



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om Product Specification
et4U.c PE3503Product Description
heThe PE3503 is a high performance monolithic UltraCMOS™
Sprescaler with a fixed divide ratio of 8. Its operating frequency
tarange is 1500 MHz to 3500 MHz. The PE3503 operates on a
anominal 3 V supply and draws only 12 mA. It is packaged in a
.Dsmall 8-lead MSOP and is ideal for microwave PLL synthesis
wsolutions.
wwThe PE3503 is manufactured in Peregrine’s patented Ultra
mThin Silicon (UTSi©) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
oCMOS.
3500 MHz Low Power UltraCMOS™
Divide-by-8 Prescaler
Features
High-frequency operation: 1500 MHz
to 3500 MHz
Fixed divide ratio of 8
Low-power operation: 12 mA typical
@ 3 V across frequency
Small package: 8-lead MSOP
U.cFigure 1. Functional Schematic Diagram
Figure 2. Package Type
8-lead MSOP
eet4IN
hPre-Amp
DQ
CLK QB
DQ
CLK QB
DQ
CLK QB
Output
Buffer
OUT
ataSTable 1. Electrical Specifications (ZS = ZL = 50 )
VDD = 3.0 V, -40° C TA 85° C, unless otherwise specified
.DParameter
Conditions
Supply Voltage
wSupply Current
wFrequency Range (FIN)
w mInput Power (PIN)
U.coOutput Power
1500 MHz Fin 3200 MHz
3200 MHz < Fin 3500 MHz
Minimum
2.85
1500
-10
0
-5
Typical
3.0
12
Maximum
3.15
17
3500
+5
+5
Units
V
mA
MHz
dBm
dBm
dBm
www.DataSheet4Document No. 70-0050-04 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7

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PE3503 pdf
PE3503
Product Specification
Evaluation Kit
Evaluation Kit Operation
The MSOP Prescaler Evaluation Board was designed
to help customers evaluate the PE3503 Divide-by-8
Prescaler. On this board, the device input (pin 2) is
connected to connector J1 through a 50 transmission
line. A series capacitor (C3) provides the necessary
DC block for the device input. It is important to note
that the value of this capacitance will impact the
performance of the device. A value of 15 pF was found
to be optimal for this board layout; other applications
may require a different value.
The device output (pin 7) is connected to connector J3
through a 50 transmission line. A series capacitor
(C1) provides the necessary DC block for the device
output. Note that this capacitor must be chosen to
have a low impedance at the desired output frequency
the device. The value of 100 pF was chosen to provide
a wide operating range for the evaluation board.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and εr of 4.4. Note
that the predominate mode for these transmission lines
is coplanar waveguide. J2 provides DC power to the
device. Starting from the lower left pin, the second pin
to the right (J2-3) is connected to the device VDD pin
(1). Two decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation. On
the board, two decoupling capacitors (C6 = 10 nF, C4 =
10 pF), located on the back of the board, perform this
function.
Applications Support
If you have a problem with your evaluation kit or if you
have applications questions call (858) 731-9400 and
ask for applications support. You may also contact us
by fax or e-mail:
Fax: (858) 731-9499
Figure 9. Evaluation Board Layouts
Peregrine Specification 101/0035
Figure 10. Evaluation Board Schematic
Peregrine Specification 102/0055
Document No. 70-0050-04 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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