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ICS9112-16 fiches techniques PDF

Integrated Circuit Systems - Low Skew Output Buffer

Numéro de référence ICS9112-16
Description Low Skew Output Buffer
Fabricant Integrated Circuit Systems 
Logo Integrated Circuit Systems 





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ICS9112-16 fiche technique
m ICS9112-16Integrated
oCircuit
.cSystems, Inc.
Low SktaeSwheOeut4tpUut BufferGeneral Description
.DaThe ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
wto align, in both phase and frequency, the REF input with
wthe CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
w133 MHz.
mICS9112-16 is a zero delay buffer that provides
osynchronization between the input and output. The
synchronization is established via CLKOUT feed back to
.cthe input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
UThe ICS9112-16 comes in an eight pin 150 mil SOIC or 173
mil TSSOP package. It has five output clocks. In the
t4absence of REF input, will be in the power down mode. In
this mode, the PLL is turned off and the output buffers are
pulled low. Power down mode provides the lowest power
econsumption for a standby condition.
Features
• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread
Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
• 3.3V ±10% operation
ataSheBlock Diagram
Pin Configuration
www.D m8 pin SOIC,TSSOP
www.DataSheet4U.co0047H—09/01/04

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