|
|
PDF QL3012 Data sheet ( Hoja de datos )
| Número de pieza | QL3012 | |
| Descripción | qASIC 3 FPGA | |
| Fabricantes | QuickLogic | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de QL3012 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
QLt3aS0h1e2ept4AUS.cIoCm3 FPGA Data Sheet• • • • • • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
.DaDevice Highlights
wwHigh Performance & High Density
w • 12,000 Usable PLD Gates with 118 I/Os
m• 300 MHz 16-bit Counters,
o400 MHz Datapaths
.c• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
UEasy to Use / Fast Development
t4Cycles
• 100% routable with 100% utilization and
complete pin-out stability
e• Variable-grain logic cells provide high
eperformance and 100% utilization
• Comprehensive design tools include high
hquality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Two global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
SAdvanced I/O Capabilities
ta• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
afor -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
.D• I/O Cells with individually controlled
Registered Input Path and Output Enables
wTotal of 118 I/O Pins
w• 110 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
w m-1/-2/-3/-4 speed grades
.co• Four High Drive input-only pins
U• Four High Drive input-only/distributed
eet4network pins
Figure 1: 320 pASIC 3 Logic Cells
www.DataSh© 2003 QuickLogic Corporation
www.quicklogic.com
•
•
•
•
1
•
•
1 page  
QL3012 pASIC 3 FPGA Data Sheet Rev F
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Table 5: Output-Only I/O Cells
Parameter
Propagation Delays (ns) Output Load
Capacitance (pF)
30 50 75 100 150
Output Delay Low to High
2.1 2.5 3.1
3.6
4.7
Output Delay High to Low
2.2 2.6 3.2
3.7
4.8
Output Delay Tri-state to High 1.2 1.7 2.2
2.8
3.9
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
Output Delay High to Tri-State a 2.0
-
-
-
-
Output Delay Low to Tri-State 1.2
-
-
-
-
a. The loads presented in Figure 2 are used for tPXZ:
1ΚΩ
tPHZ
5 pF
1ΚΩ
tPLZ
5 pF
Figure 2: Loads used for tPXZ
© 2003 QuickLogic Corporation
•
www.quicklogic.com ••
•
••
5
5 Page 
QL3012 pASIC 3 FPGA Data Sheet Rev F
The 1149.1 standard requires the following three tests:
• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload
Instruction), and input boundary cells capture the input data for analysis.
• Sample/Preload Instruction. This instruction allows a device to remain in its
functional mode, while selecting the boundary scan register to be connected between
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a
data scan operation, allowing users to sample the functional data entering and leaving
the device.
• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary
scan entirely, so the data passes through the bypass register. The Bypass instruction
allows users to test a device without passing through other devices. The bypass register
is connected between the TDI and TDO pins, allowing serial data to be transferred
through a device without affecting the operation of the device.
© 2003 QuickLogic Corporation
•
www.quicklogic.com ••
•
••
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet QL3012.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| QL3012 | qASIC 3 FPGA | QuickLogic |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |