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PDF NCP5351 Data sheet ( Hoja de datos )
| Número de pieza | NCP5351 | |
| Descripción | 4A Synchronous Buck Power MOSFET Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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N4PoCAwPS5ey3rnS5Mch1eOherSto4FnUEo.cTuosmDBriuvecrkThe NCP5351 is a dual MOSFET gate driver optimized to drive the
tagates of both high−side and low−side Power MOSFETs in a
Synchronous Buck converter. The NCP5351 is an excellent
acompanion to multiphase controllers that do not have integrated gate
.Ddrivers, such as ON Semiconductor’s CS5323, CS5305 or CS5307.
wThis architecture provides a power supply designer the flexibility to
wlocate the gate drivers close to the MOSFETs.
w The 4.0 A drive capability makes the NCP5351 ideal for minimizing
switching losses in MOSFETs with large input capacitance. Optimized
minternal, adaptive nonoverlap circuitry further reduces switching
olosses by preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
.cvoltages as high as 25 V. Both gate outputs can be driven low, and
supply current reduced to less than 25 mA, by applying a low logic
level to the Enable (EN) pin. An undervoltage lockout function
Uensures that both driver outputs are low when the supply voltage is
t4low, and a thermal shutdown function provides the IC with
overtemperature protection.
The NCP5351 is pin−to−pin compatible with the SC1205 and is
eavailable in a standard SO−8 package and thermally enhanced
eDFN−10.
hFeatures
• 4.0 A Peak Drive Current
S• Rise and Fall Times < 15 ns Typical into 6000 pF
ta• Propagation Delay from Inputs to Outputs < 20 ns
• Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
• Floating Top Driver Accommodates Applications Up to 25 V
a• Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
.D• Thermal Shutdown Protection Against Overtemperature
• < 1.0 mA Quiescent Current − Enabled
w• 25 mA Quiescent Current − Disabled
• Internal TG to DRN Pulldown Resistor Prevents HV Supply−Induced
wTurn On of High−Side MOSFET
w heet4U.com• Pb−Free Package is Available
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8
1
1
SO−8
D SUFFIX
CASE 751
DFN−10
MN SUFFIX
CASE 485C
MARKING
DIAGRAMS
8
5351
ALYW
1
10
5351
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
PIN CONNECTIONS
1
DRN
TG
BST
CO
SO−8
8
PGND
BG
VS
EN
1
DRN
TG
N/C
BST
CO
DFN−10
10
GND
BG
N/C
VS
EN
ORDERING INFORMATION
Device
Package
Shipping†
NCP5351D
SO−8
98 Units/Rail
NCP5351DR2
SO−8 2500 Tape & Reel
NCP5351MNR2
NCP5351MNR2G
DFN−10
DFN−10
(Pb−Free)
2500 Tape & Reel
2500 Tape & Reel
S†For information on tape and reel specifications,
taincluding part orientation and tape sizes, please
arefer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.D© Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
November, 2004 − Rev. 11
NCP5351/D
1 page  
NCP5351
ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C; VS = 5.0 V; 4.0 V < VBST < 25 V; VEN = VS; unless otherwise noted)
Parameter
Test Conditions
Min Typ Max
DC OPERATING SPECIFICATIONS
POWER SUPPLY
VS Quiescent Current, Operating
VBST Quiescent Current, Operat-
ing
VCO = 0 V, 4.5 V; No output switching
VCO = 0 V, 4.5 V; No output switching
− 1.0 −
− 50 −
Quiescent Current, Non−Operat-
ing
VEN = 0 V; VCO = 0 V, 4.5 V
− − 25
Undervoltage Lockout
Start Threshold
CO = 0 V
4.05 4.25 4.48
Hysteresis
CO = 0 V
− 275 −
CO INPUT CHARACTERISTICS
High Threshold
−
2.0 −
−
Low Threshold
− − − 0.8
Input Bias Current
EN INPUT CHARACTERISTICS
0 < VCO < VS
− 0 1.0
High Threshold
Both outputs respond to CO
2.0 −
−
Low Threshold
Both outputs are low, independent of CO
− − 0.8
Input Bias Current
THERMAL SHUTDOWN
0 < VEN < VS
− 0 10
Overtemperature Trip Point
− − 170 −
Hysteresis
− − 30 −
HIGH−SIDE DRIVER
Peak Output Current
− − 4.0 −
Output Resistance (Sourcing)
Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125°C,
−
0.5
−
VBST − VDRN = 4.5 V, VTG = 4.0 V + VDRN
Output Resistance (Sinking)
Duty Cycle < 2.0%, Pulse Width < 100 ms,
− 0.42 −
TJ = 125°C, VBST − VDRN = 4.5 V, VTG = 0.5 V + VDRN
LOW−SIDE DRIVER
Peak Output Current
− − 4.0 −
Output Resistance (Sourcing)
Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125°C,
−
0.6
−
VS = 4.5 V, VBG = 4.0 V
Output Resistance (Sinking) Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125°C, − 0.42 −
VS = 4.5 V, VBG = 0.5 V
Unit
mA
mA
mA
V
mV
V
V
mA
V
V
mA
°C
°C
A
W
W
A
W
W
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5
5 Page 
NCP5351
TYPICAL PERFORMANCE CHARACTERISTICS
+5.0 V
R1
1.0 k
Gated
Pulse
Burst (2)
+
−
VS
BST
EN TG
CO DRN
BG
PGND
R2
50
C4
100 nF
C2
10 mF
Input
Pulse
+
−
C1
10 mF
C3
100 nF
4.0 V DRN
CO
TG
BG
tpdlBG
tpdlTG
tpdhTG
(non−overlap)
tpdhBG
(non−overlap)
Figure 13. Nonoverlap Test Configuration
Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF;
Room Temperature.
Figure 14. Top Gate Rise Time
Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF;
Room Temperature.
Figure 15. Top Gate Fall Time
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11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NCP5351.PDF ] | |
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