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PDF ADSP2191M Data sheet ( Hoja de datos )
| Número de pieza | ADSP2191M | |
| Descripción | DSP Microcomputer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
DSP Microcomputer
ADSP-2191M
PERFORMANCE FEATURES
6.25 ns Instruction Cycle Time, for up to 160 MIPS
Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-
www.DataSheet4U.computation and Memory Instructions
Instruction Cache Allows Dual Operand Fetches in Every
Instruction Cycle
Multifunction Instructions
Pipelined Architecture Supports Efficient Code
Execution
Architectural Enhancements for Compiled C and C++
Code Efficiency
Architectural Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, and Peripherals
Flexible Power Management with User-Selectable
Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
ADSP-219x
DSP CORE
CACHE
64 ؋ 24-BIT
ADDRESS
24 BIT
DATA
ADDRESS 24 BIT
DATA
ADDRESS 16 BIT
DATA
ADDRESS
16 BIT
DATA
JTAG
TEST &
EMULATION
6
DAG1
4 ؋ 4 ؋ 16
DAG2
4 ؋ 4 ؋ 16
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
24
DMA
CONNECT
PM DATA BUS
PX
24
DM DATA BUS
16
DATA
REGISTER
FILE
INPUT
REGISTERS
MULT
RESULT
REGISTERS
16 ؋ 16-BIT
BARREL
SHIFTER
ALU
EXTERNAL PORT
I/O ADDRESS 18
24 DMA ADDRESS
24 DMA DATA
16 I/O DATA
ADDR BUS
MUX
DATA BUS
MUX
I/O PROCESSOR
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
DMA
CONTROLLER
HOST PORT
SERIAL PORTS
(3)
SPI PORTS
(2)
SYSTEM INTERRUPT CONTROLLER
UART PORT
(1)
PROGRAMMABLE
FLAGS (16)
TIMERS (3)
22
16
24
18
6
2
3
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2002
1 page  
Three programmable interval timers generate periodic inter-
rupts. Each timer can be independently set to operate in one of
three modes:
• Pulse Waveform Generation mode
• Pulsewidth Count/Capture mode
• External Event Watchdog mode
Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer’s configuration register enables or
disables the corresponding timer independently of the others.
www.DataSheet4U.com
Memory Architecture
The ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page 0 in the DSP’s memory map. In addition to the
ADSP-2191M
internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.
As shown in Figure 2, the DSP’s two internal memory blocks
populate all of Page 0. The entire DSP memory map consists of
256 pages (Pages 0−255), and each page is 64K words long.
External memory space consists of four memory banks (banks
0–3) and supports a wide variety of SRAM memory devices. Each
bank is selectable using the memory select pins (MS3–0) and has
configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page 255 while the remaining 254 pages are addressable off-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their
own select pin (IOMS). Pages 0–7 of I/O memory space reside
on-chip and contain the configuration registers for the peripher-
als. Both the core and DMA-capable peripherals can access the
DSP’s entire memory map.
INTERNAL
MEMORY
EXTERNAL
MEMORY
(16- BIT)
INTERNAL
MEMORY
64K WORD
MEMORY
PAGES
PAGE 255
RESERVED
BOOT ROM, 24-BIT
LOGICAL
ADDRESS
0؋FF FFFF
0؋FF 0400
0؋FF 03FF
0؋FF 0000
PAGES 192–254
BANK3
(MS3)
0؋C0 0000
PAGES 128–191
BANK2
(MS2)
PAGES 64–127
BANK1
(MS1)
0؋80 0000
0؋40 0000
PAGES 1–63
BANK0
(MS0)
BLOCK3, 16-BIT
BLOCK2, 16-BIT
PAGE 0
BLOCK1, 24-BIT
BLOCK0, 24-BIT
0؋01 0000
0؋00 C000
0؋00 8000
0؋00 4000
0؋00 0000
Figure 2. Memory Map
Internal (On-Chip) Memory
The ADSP-2191M’s unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly
LOWER PAGE BOUNDARIES
ARE CONFIGURABLE FOR
BANKS OF EXTERNAL MEMORY.
BOUNDARIES SHOWN ARE
BANK SIZES AT RESET.
MEMORY SELECTS (MS)
FOR PORTIONS OF THE
MEMORY MAP APPEAR
WITH THE SELECTED
MEMORY.
BOOT MEMORY
16-BIT
(BMS)
64K WORD
LOGICAL
ADDRESS
0؋FE FFFF
PAGES 1–254
0؋01 0000
I/O MEMORY
16- BIT
1K WORD
PAGES 8–255
1K WORD
PAGES 0–7
LOGICAL
ADDRESS
0؋FF 3FF
EXTERNAL
(IOMS)
INTERNAL
0؋08 000
0؋07 3FF
0؋00 000
8-BIT 10-BIT
REV. 0
–5–
5 Page 
ADSP-2191M
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after the
IDLE.
Clock Signals
The ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a
1 M Ω shunt resistor connected as shown in Figure 3. Capacitor
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
www.DataSheet4Uqu.ceonmcy, microprocessor-grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP’s CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.
The DSP provides a user-programmable 1؋ to 32؋ multiplica-
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL6–0, BYPASS, and DF pins decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be con-
trolled in software. The combination of pullup and pull-down
resistors in Figure sets up a core clock ratio of 6:1, which
produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the ADSP-219x/2191 DSP
Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2191M operate at the rate
set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is 160 MHz and the maximum periph-
eral clock is 80 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
Reset
The RESET signal initiates a master reset of the ADSP-2191M.
The RESET signal must be asserted during the powerup
sequence to assure proper initialization. RESET during initial
powerup must be held long enough to allow the internal clock to
stabilize.
The powerup sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied
to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100 µs
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the
RESET signal should be held low. On any subsequent resets, the
RESET signal must meet the minimum pulsewidth specifica-
tion, tWRST.
1M⍀
VDD
VDD
RUNTIME
PF PIN I/O
25MHz
CLKIN
XTAL
CLKOUT
MSEL0 (PF0)
ADSP-2191M
MSEL1 (PF1)
MSEL2 (PF2)
MSEL3 (PF3)
MSEL4 (PF4)
RESET
SOURCE
MSEL5 (PF5)
MSEL6 (PF6)
DF (PF7)
BYPASS
RESET
THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASS PINS
SELECT THE CORE CLOCK
RATIO.
HERE, THE SELECTION (6:1)
AND 25MHz INPUT CLOCK
PRODUCE A 150MHz CORE
CLOCK.
Figure 3. External Crystal Connections
The RESET input contains some hysteresis. If using an RC
circuit to generate your RESET signal, the circuit should use an
external Schmidt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When RESET is released, if
there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF 0000).
Power Supplies
The ADSP-2191M has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply must be connected to a 3.3 V supply. All external
supply pins must be connected to the same supply.
Powerup Sequence
Power up together the two supplies VDDEXT and VDDINT. If
they cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.
Booting Modes
The ADSP-2191M has five mechanisms (listed in Table 6) for
automatically loading internal program memory after reset. Two
No-boot modes are also supported.
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet ADSP2191M.PDF ] | |
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