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PDF ICS9148-11 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-11 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 11
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
TheICS9148-11 generates all clocks required for high speed RISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.
High drive BCLK outputs typically provide greater than 1V/ns slew
rate into 30 pF loads. PCLK outputs typically provide better than 1V/
ns slew rate into 20 pF loads while maintaining50±5% duty cycle.
The REF clock outputs typically provide better than 0.5V/ns slew
rates.
Features
Generates four processor, six bus, one 14.31818MHz and 12
SDRAM clocks.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on BUS clocks.
CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
Test clock mode eases system design
Custom configurations available
VDD(1:3) - 3.3V ±10%
(inputs 5V tolerant w/series R )
VDDL(1:2) - 2.5V or 3.3V ±5%
PC serial configuration interface
Power Management Control Input pins
48-pin SSOP package
Block Diagram
Pin Configuration
9148-11 RevB 12/09/97P
48-Pin SSOP
Functionality
CPUCLK,
OE SDRAM
(MHz)
0 High-Z
1 66.6
X1, REF
(MHz)
High-Z
14.318
PCICLK
(MHz)
High-Z
33.3
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9148 - 11
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
D2(H)
B. The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte 0
ACK
Byte 1
ACK Byte 0, 1, 2, etc in sequence until STOP.
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (Default=0)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
DESCRIPTION
Reserved
Must be 0 for normal operation
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
Must be 0 for normal operation
In Spread Spectrum, Controls Spreading
(0=1.8%, 1=0.6%)
Reserved
Reserved
Bit1 Bit0
1 1 - Tri-State
1 0 - Spread Spectrum Enable
0 1 - Testmode
0 0 - Normal operation
PWD
0
0
0
0
0
0
0
0
0
0
Note: PWD = Power-Up Default
5
5 Page 
ICS9148 - 11
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Operating
Supply Current
IDD2.5OP CL = 0 pF; Select @ 66M
6 8 9.5
Skew1
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
TREF-IOAPIC VT = 1.5 V; VTL = 1.25 V; CPU Leads
250 500
12 4
860
1Guarenteed by design, not 100% tested in production.
UNITS
mA
ps
ns
ps
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
SYMBOL
RDSP
2
1
B
RDSN
1
2B
CONDITIONS
VO = VDD*(0.5)
VO = VDD*(0.5)
MIN
15
15
TYP
Output High Voltage VOH2B IOH = -12.0 mA
2 2.6
Output Low Voltage VOL2B IOL = 12 mA
0.3
Output High Current
IOH2B VOH = 1.7 V
-25
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
IOL2B
tr2B1
tf2B1
dt2
1
B
tsk2B1
tjcyc-cy
1
c2B
tj1s2B1
tjab
1
s2B
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
19 26
1.7
1.5
45 50
60
150
30
-250 80
1Guarenteed by design, not 100% tested in production.
MAX UNITS
45 Ω
45 Ω
V
0.4 V
-16 mA
mA
2 ns
2 ns
55 %
250 ps
250 ps
150 ps
+250 ps
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-11.PDF ] | |
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