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PDF ICS9148-26 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-26 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 26
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-26 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include two CPU, six PCI and fourteen SDRAM clocks.
Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.5% or ±1.5% modulation to reduce the
EMI. Serial programming I2C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PIC, CPU, DIMM). The
add on card might have a pull up or pull down.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns.
No external load cap for CL=18pF crystals
±250 ps CPU, PCI clock skew
250ps (cycle to cycle) CPU jitter @ 66.66MHz
Smooth frequency switch, with selections from 50 to
133 MHz CPU.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<6ns propagation delay SDRAM form Buffer Input
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates into 20pF.
Block Diagram
9148-26 Rev D 07/23/98
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:13), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:1)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
SDRAM13 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
14
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
26
25
-
21,20,18,17
32,31,29,28
38,37,35,34
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
48MHz (Act/Inact)
24 MHz (Act/Inact)
(Reserved)
SDRAM (8:11) (Active/Inactive)
(SDRAM 10, 11 only in Desktop Mode, MODE=1)
SDRAM (4:7) (Active/Inactive)
SDRAM (0:3) (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
5
ICS9148 - 26
5 Page 
ICS9148 - 26
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
2 VDD+0.3 V
Input Low Voltage
VIL
VSS-0.3
0.8 V
Supply Current
IDD CL = 0 pF; Select @ 66M
77 180 mA
IDDL
6.0 30 mA
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
14.318
5
MHz
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
CINX
Ttrans
Ts
TSTAB
TCP U-BUS
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
27 36 45 pS
1.5 3 mS
mS
3 mS
1.0 2.2 4.0 nS
1Guarenteed by design, not 100% tested in production.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-26.PDF ] | |
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