PDF ICS9148-32 Data sheet ( Hoja de datos )

Número de pieza	ICS9148-32
Descripción	Pentium/ProTM System Clock Chip
Fabricantes	Integrated Circuit Systems
Logotipo
Hay una vista previa y un enlace de descarga de ICS9148-32 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas
No Preview Available ! Integrated Circuit Systems, Inc. ICS9148-32 Pentium/ProTM System Clock Chip General Description The ICS9148-32 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up. PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks. Serial I2C interface allows power management by output clock disabling. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Features Generates system clocks for CPU, IOAPIC, PCI, 14.314 MHz REF , USB, and Super I/O Supports single or dual processor systems I2C interface Supports Spread Spectrum modulation for CPU & PCI clocks, ±0.255% Center Spread or 0 to -0.6% Down Spread. Skew from CPU (earlier) to PCI clock 1 to 4ns CPU cycle to cycle jitter ±200ps 2.5V or 3.3V output: CPU, IOAPIC 3.3V outputs: PCI, REF, 48MHz No power supply sequence requirements Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal 48 pin 300 mil SSOP Pin Configuration The ICS9148-32 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply. Block Diagram Pentium is a trademark on Intel Corporation. 9148-32 Rev B 09/09/98 48-Pin SSOP Power Groups VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz, 24/48MHz# VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3) Ground Groups GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 = PCICLK_F, PCICLK (0:6) GND3 = 48MHz, 24/48MHz# GNDL1 = IOAPIC (0:1) GNDL2 = CPUCLK (0:3) ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 1 page ICS9148-32 Power Management Clock Enable Configuration CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK XX 00 01 10 11 0 Low 1 Low 1 Low 1 100/66.6MHz 1 100/66.6MHz PCICLK Low Low 33.3 MHz Low 33.3 MHz Other Clocks, REF, IOAPICs, 48 MHz 0 48 MHz 1 Stopped Running Running Running Running Crystal Off Running Running Running Running VCOs Off Running Running Running Running Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9148-32 Power Management Requirements SIGNAL SIGNAL STATE CPU_ STOP# PCI_STOP# PD# 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 Latency No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independent of these. 5 5 Page ICS9148-32 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage Output Low Voltage Output High Current VOH2B VOL2B IOH2B IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V 2 2.3 V 0.2 0.4 V -41 -19 mA Output Low Current IOL2B VOL = 0.7 V Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V Fall Time tf2B1 VOH = 2.0 V, VOL = 0.4 V Duty Cycle dt2 1 B VT = 1.25 V Skew tsk2B1 VT = 1.25 V Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.25 V Jitter, One Sigma Jitter, Absolute tj1s2B1 tjabs2B1 VT = 1.25 V VT = 1.25 V 1Guaranteed by design, not 100% tested in production. 19 37 mA 1.25 1.6 ns 1 1.6 ns 45 48 55 % 30 175 ps 150 250 ps 40 150 ps -250 140 +250 ps Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH4B IOH = -18 mA Output Low Voltage VOL4B IOL = 18 mA Output High Current IOH4B VOH = 1.7 V Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew1 Jitter, One Sigma1 Jitter, Absolute1 IOL4B Tr4B Tf4B Dt4B tsk4B1 Tj1s4B Tjabs4B VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V 1Guaranteed by design, not 100% tested in production. MIN 2 29 45 -5 TYP MAX UNITS 2.2 V 0.33 0.4 V -41 -28 mA 37 mA 1.3 1.6 ns 1.1 1.6 ns 54 55 % 60 250 ps 1 3% 5% 11 11 Page

Páginas	Total 14 Páginas
PDF Descargar	[ Datasheet ICS9148-32.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ICS9148-32	Pentium/ProTM System Clock Chip	Integrated Circuit Systems
ICS9148-36	Frequency Generator & Integrated Buffers	Integrated Circuit Systems
ICS9148-37	Frequency Generator & Integrated Buffers	Integrated Circuit Systems

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar