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PDF ICS9148-47 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-47 | |
| Descripción | Pentium/ProTM System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148-47
Pentium/ProTM System Clock Chip
General Description
The ICS9148-47 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz,
and one selectable 48/24MHz.
Features
Generates system clocks for CPU, PCI, IOAPIC ,
14.314 MHz, 48 and 24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU, IOAPIC
3.3V outputs: PCI, REF
No power supply sequence requirements
28 pin SOIC
Spread Sectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
9148-47 Rev D 08/04/98
28 pin SOIC
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = 48MHz
VDDL = CPUCLK (0:1)
VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz
GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9148-47
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
2 VDD+0.3 V
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
VIL
VSS-0.3
0.8 V
IIH VIN = VDD
0.1 5 µA
IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2.0
µA
IIL2 VIN = 0 V; Inputs with pull-up resistors
-200 -100
µA
Operating
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
60 170 mA
Supply Current
Power Down
Supply Current
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
66 170
3 650 µA
Input frequency
Input Capacitance1
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
Fi
CIN
CINX
Ttrans
Ts
TSTAB
TAGP-PCI1
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
14.318
5
27 36 45
3
5
3
1 3.5 4
MHz
pF
pF
ms
ms
ms
ns
1Guaranteed by design, not 100% tested in production.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-47.PDF ] | |
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