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PDF ICS9148-53 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-53 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 53
Frequency Generator & Integrated Buffers for Mother Boards
General Description
Features
The ICS9148-53 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 150MHz.
PentiumPro, AMD or Cyrix. Sixteen different reference
- 7 PCI(3.3V) (including one free
frequency multiplying factors are externally selectable with
running PCICLK)
smooth frequency transitions.
- 2AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 150MHz
Spread spectrum may be enabled through I2C programming.
- 1 REF (3.3V) @ 14.318MHz
- 1 Fixed clock 3.3V @ 48MHz
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to Skew characteristics:
board design iterations or costly shielding. The ICS9148-53
employs a proprietary closed loop design, which tightly
- CPU CPU<250ps
- CPU(early) PCI : 1-4ns
controls the percentage of spreading over process and Supports Spread Spectrum modulation & I2C
temperature variations.
programming for Power Management, Frequency Select
Serial programming I2C interface allows changing functions,
Efficient Power management scheme through power
down CPU, PCI,AGP and CPU_STOP clocks.
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip Uses external 14.318MHz crystal
PLL.
Block Diagram
48 pin 300mil SSOP.
Read back of FS pin values from I2C
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 =AGP(1:2)
VDD5 = Fixed PLL, 48MHz ,AGP0
VDDL= CPUCLK(0:3)
9148-53 Rev C 08/14/98
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9148 - 53
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
D2(H)
B. The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
Byte Count
Readback
Then Byte 0, 1, 2, etc. in
ACK sequence until STOP.
D3(H)
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F. To simplify the clock generator I2C interface, the protocol is set to use only "Block Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G. The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running,
except in Tristate Mode.
H. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1
(Enabled output state).
5
5 Page 
ICS9148 - 53
Shared Pin Operation -
Input/Output Pins
Pins 2, 7, 8, 25 and 26 on the ICS9148-53 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
11
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| PDF Descargar | [ Datasheet ICS9148-53.PDF ] | |
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