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PDF ICS9148-58 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-58 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 58
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-58 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-58
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0)
Block Diagram
Features
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU orAGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Spread Spectrum 0 to -5% down spread.
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
9148-58 Rev C 12/07/98
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9148 - 58
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
15
14
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
47
-
-
46
2
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5
5 Page 
ICS9148 - 58
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage VOH2A IOH = -28 mA
Output Low Voltage VOL2A IOL = 27 mA
Output High Current IOH2A VOH = 2.0 V
Output Low Current
IOL2A VOL = 0.8 V
Rise Time
tr2A1 VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf2A1 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt2A1 VT = 1.5 V
Skew
tsk2A1 VT = 1.5 V
Jitter, One Sigma
Jitter, Absolute
tj1s2A1
tjabs2A1
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
2.5 2.6
V
0.35 0.4 V
-29 -23 mA
33 37
mA
1.75 2
ns
1.1 2 ns
45 50 55 %
50 250 ps
65 150 ps
-250 165 250 ps
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PAR AM ETER
SYM B OL
C ONDIT IONS
MIN TYP
Output High Voltage VOH2B IOH = -8 mA
2
Output Low Voltage VOL2B IOL = 12 mA
Output High Current IOH2B VOH = 1.7 V
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
IOL 2 B
t r2 B 1
t f2 B 1
dt2B1
tsk2B1
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
VT = 1.25 V
19
40
Jitter, Single Edge
Displacement2
Jitter, One Sigma
Jitter, Absolute
tjsed2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
-3 0 0
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
2 .2
0 .3
-2 0
26
1 .5
1 .6
47
60
200
65
160
M AX UNITS
V
0.4 V
-16 mA
mA
1.8 ns
1.8 ns
55 %
250 ps
250 ps
150 ps
300 ps
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-58.PDF ] | |
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